x2 Active Multiplier SMT, 27 - 31 GHz Fout Features: Very High Output Power: +20 dBm Low Input Power Drive: -2 to +6 dBm Very High Fo, 3Fo Isolation: >55 dBc @ Fout= 29 GHz 100 kHz SSB Phase Noise: -128 dBc/Hz Single Supply: +5V @ 213 mA 24 Lead 4×4mm QFN Package: 16mm2

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

10 W (40 dBm), 0.01 GHz to 1.1 GHz, GaN Power Amplifier Features: High small signal gain: 20 dB typical POUT: 41.5 dBm typical at PIN = 27 dBm High PAE: 60% typical at PIN = 27 dBm Instantaneous bandwidth: 0.01 GHz to 1.1 GHz across all frequencies Supply voltage: VDD = 28 V at a quiescent current of 100 mA Internal prematching Simple and compact external tuning for optimal performance 5 mm × 5 mm, 32-lead LFCSP

Low Noise Amplifier SMT, 21 - 29 GHz Features: Noise Figure: 2.5 dB Gain: 13 dB Supply: +3V @ 35mA 50 Ohm Matched Input/Output RoHS Compliant 3x3 mm SMT Package

Low Noise Amplifier SMT, 350 - 550 MHz Features: Noise Figure: ≤1 dB Output IP3: +38 dBm Gain: 17 dB Very Stable Gain vs. Supply & Temp Single Supply: +5V @ 104 mA 50 Ohm Matched Output

InGaP HBT Divide-by-4 SMT, DC - 18 GHz Features: Ultra Low SSB Phase Noise: -150 dBc/Hz Very Wide Bandwidth Output Power: -4 dBm Single DC Supply: +5V 3x3 mm QFN SMT Package

Dual Output Low Noise Amplifier, 0.04 - 0.96 GHz Features: Single-ended or Balanced Output High Output IP3: +27 dBm Low Noise Figure: 3.5 dB Single Positive Supply: +5V 75 Ohm Input

HBT Vector Modulator SMT, 700 - 1000 MHz Features: Continuous Phase Control: 360° Continuous Gain Control: 40 dB Low Output Noise Floor: -162 dBm/Hz High Input IP3: +34 dBm 16 Lead 3×3mm SMT Package: 9mm2

LNA with Failsafe Bypass Mode SMT, 1700 - 2200 MHz Features: Noise Figure: 1.4 dB Output IP3: +29 dBm Gain: 17 dB Failsafe Operation: Bypass is enabled when LNA is unpowered Single Supply: +3V or +5V 16 Lead 3x3mm SMT Package: 9mm²

Fractional-N PLL with Integrated VCO SMT, 1.31 - 5.66 GHz Features: Ultra Low Phase Noise -112 dBc/Hz in Band Typ. Figure of Merit (FOM) -230 dBc Integer <180 fs RMS Jitter  24-Bit Step Size, 3 Hz Resolution Typ.  Exact Frequency Mode Built in Digital Self Test  40 Lead 6x6mm SMT Package: 36mm²