The ADRV9029 is a highly integrated, radio frequency (RF) agile transceiver offering four independently controlled transmitters, dedicated observation receiver inputs for monitoring each transmitter channel, four independently controlled receivers, integrated synthesizers, and digital signal processing functions providing a complete transceiver solution. The device provides the performance demanded by cellular infrastructure applications, such as small cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations.The receiver subsystem consists of four independent, wide bandwidth, direct conversion receivers with wide dynamic range. The four independent transmitters use a direct conversion modulator resulting in low noise operation with low power consumption. The device also includes two wide bandwidth, time shared, observation path receivers with two inputs each for monitoring transmitter outputs.The complete transceiver subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. Other auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/ outputs (GPIOs) that provide an array of digital control options are also integrated.To achieve a high level of RF performance, the transceiver includes five fully integrated phase-locked loops (PLLs). Two PLLs provide low noise and low power fractional-N RF synthesis for the transmitter and receiver signal paths. A third fully integrated PLL supports an independent local oscillator (LO) mode for the observation receiver. The fourth PLL generates the clocks needed for the converters and digital circuits, and a fifth PLL provides the clock for the serial data interface.A multichip synchronization mechanism synchronizes the phase of all LOs and baseband clocks between multiple ADRV9029 chips. All voltage controlled oscillators (VCOs) and loop filter components are integrated and adjustable through the digital control interface.This device contains a fully integrated, low power digital predistortion (DPD) adaptation engine for use in power amplifier linearization. DPD enables use of high efficiency power amplifiers, reducing the power consumption of base station radios while also reducing the number of SERDES lanes necessary to interface with baseband processors.The low power crest factor reduction (CFR) engine of the ADRV9029 reduces the peak to average ratio (PAR) of the input signal, enabling higher efficiency transmit line ups while reducing the processing load on baseband processors.The serial data interface consists of four serializer lanes and four deserializer lanes. The interface supports both the JESD204B and JESD204C standards, operating at data rates up to 24.33 Gbps. The interface also supports interleaved mode for lower bandwidths, thus reducing the number of high speed data interface lanes to one. Both fixed and floating-point data formats are supported. The floating-point format allows internal automatic gain control (AGC) to be invisible to the demodulator device.The ADRV9029 is powered directly from 1.0 V, 1.3 V, and 1.8 V regulators and is controlled via a standard serial peripheral interface (SPI) serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9029 is packaged in a 14 mm ? 14 mm, 289-ball chip scale ball grid array (CSP_BGA).APPLICATIONS3G/4G/5G TDD and FDD massive MIMO, macro and small cell base stations

The AD9371 is a highly integrated, wideband RF transceiveroffering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The ICdelivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTSequipment in both FDD and TDD applications. The AD9371operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signalpaths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digitalfilters, eliminating the need for these functions in the digitalbaseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integratedto provide additional monitoring and control capability.An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis forthe transmitter, the receiver, the observation receiver, and theclock sections. Careful design and layout techniques provide theisolation demanded in high performance base station applications.All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, anda standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitterand auxiliary converter performance. The AD9371 is packaged in a12 mm ? 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells? FDD and TDD active antenna systems? Microwave, nonline of sight (NLOS) backhaul systems

RF Amplifier Low Noise Amplifier, LNA

The HMC407MS8G & HMC407MS8GE are high?efficiency GaAs InGaP Heterojunction Bipolar?Transistor (HBT) MMIC Power amplifiers which?operate between 5 and 7 GHz. The amplifier requires?no external matching to achieve operation and is?thus truly 50 Ohm matched at input and output. The?amplifier is packaged in a low cost, surface mount?8 leaded package with an exposed base for improved?RF and thermal performance. The amplifier?provides 15 dB of gain, +29 dBm of saturated power?at 28% PAE from a +5V supply voltage. Power down?capability is available to conserve current consumption?when the amplifier is not in use.Applications UNII HiperLAN

The HMC415LP3(E) is a high efficiency GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC Power amplifier which operates between 4.9 and 5.9 GHz. The amplifier is packaged in a low cost, leadless surface mount package with an exposed base for improved RF and thermal performance. With a minimum of external components, the amplifier provides 20 dB of gain, +26 dBm of saturated power, and 34% PAE from a +3V supply voltage. Vpd can be used for full power down or RF output power/current control. For +15 dBm OFDM output power (64 QAM, 54 Mbps), the HMC415LP3(E) achieves an error vector magnitude (EVM) of 3.7% meeting 802.11a linearity requirements.Applications 802.11a WLAN HiperLAN WLAN Access Points UNII & ISM Radios

The HMC439QS16G(E) is a digital phase-frequency detector intended for use in low noise phase-locked loop applications for inputs from 10 to 1300 MHz. Its combination of high frequency of operation along with its ultra low phase noise floor make possible synthesizers with wide loop bandwidth and low N resulting in fast switching and very low phase noise. When used in conjunction with a differential loop amplifier, the HMC439QS16G(E) generate output voltages that can be used to phase lock a VCO to a reference oscillator. The device is packaged in a low cost, surface mount 16 lead QSOP package with an exposed base for improved RF and thermal performance.APPLICATIONS Point-to-Point Radios Satellite Communication Systems Military Applications Sonet Clock Generation

The HMC472ALP4E are broadband 6-bit GaAs IC digital attenuators in low cost leadless surface mount packages. This single positive control line per bit digital attenuator incorporates off chip AC ground capacitors for near DC operation, making it suitable for a wide variety of RF and IF applications. Covering DC to 3.8 GHz, the insertion loss is less than 2.0 dB typical. The attenuator bit values are 0.5 (LSB), 1, 2, 4, 8, and 16 dB for a total attenuation of 31.5 dB. Attenuation accuracy is excellent at ? 0.25 dB typical step error with an IIP3 of +54 dBm. Six TTL/CMOS control inputs are used to select each attenuation state. A single Vdd bias of +5V is required.APPLICATIONSThe HMC472ALP4E is ideal for: 3G Infrastructure & access points? Cellular/3G, LTE & UMB WiMAX, WiBN & Fixed Wireless? Test Equipment and Sensors GSM, WCDMA & TD-SCDMA

The HMC356LP3(E) is a high dynamic range GaAs PHEMT MMIC Low Noise Amplifier is ideal for GSM & CDMA cellular basestation and Mobile Radio front-end receivers operating between 350 and 550 MHz. This LNA has been optimized to provide 1 dB noise figure, 17 dB gain and +38 dBm output IP3 from a single supply of +5V @ 104 mA. Input and output return losses are 15 dB typical, with the LNA requiring only four external components to optimize the RF input match, RF ground and DC bias.Applications GSM 450 & GSM 480 CDMA 450 Private Land Mobile Radio

The HMC368LP4(E) is a miniature amp-doubler-amps utilizing GaAs PHEMT technology in 4 ? 4 mm leadless surface mount package. When driven by a +2 dBm signal, the multiplier provides +15 dBm typical output power from 9 to 16 GHz. The Fo and the 3Fo isolations are 18 dB typical. The low additive SSB phase noise of ?140 dBc/Hz at 100 kHz offset helps the user maintain good system noise performance. The HMC368LP4(E) is ideal for use in LO multiplier chains allowing reduced parts count vs. traditional approaches.APPLICATIONS Microwave Radios & VSAT Fiber Optic Infrastructure Military Communications & Radar

The HMC601LP4(E) Logarithmic Detector/Controller converts RF signals at its input, to a proportional DC voltage at its output. The HMC601LP4(E) employ a successive compression topology which delivers extremely high dynamic range and conversion accuracy over a wide input frequency range. As the input power is increased, successive amplifiers move into saturation one by one creating an accurate approximation of the logarithm function.The output of a series of square law detectors is summed, converted into voltage domain and buffered to drive the LOGOUT output. For detection mode, the LOGOUT pin is shorted to the VSET input, and will provide a nominal logarithmic slope of 19mV/dB and an intercept of -100 dBm. The HMC601LP4(E) can also be used in the controller mode where an external voltage is applied to the VSET pin, to create an AGC or APC feedback loop. The HMC601LP4(E) provides a 15/34ns (rise/fall time) response time enabling RF burst detection to a pulse rate beyond 20 MHz.Applications Cellular/PCS/3G WiMAX, WiBro & Fixed Wireless Power Monitoring & Control Circuitry Receiver Signal Strength Indication (RSSI) Automatic Gain & Power Control Circuits