Attenuators 0.5 dB LSB 5-Bit DATT 0.7 - 3.8 GHz

RF Amplifier lo Noise amp SMT, 2 - 12 GHz

Attenuators 0.5dB LSB 5-Bit DATT 0.7 - 3.8 GHz

RF Amplifier Low Noise Amplifier SMT,5-10 GHz

The AD8313 is a complete multistage demodulating logarithmic amplifier that can accurately convert an RF signal at its input to an equivalent decibel-scaled value at its dc output. The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz. Application is straightforward, requiring only a single supply of 2.7 V to 5.5 V and the addition of a suitable input and supply decoupling. Operating on a 3 V supply, its 13.7 mA consumption (for TA = 25°C) is only 41 mW. A power-down feature is provided; the input is taken high to initiate a low current (20 µA) sleep mode, with a threshold at half the supply voltageThe AD8313 is fabricated on Analog Devices, Inc., advanced 25 GHz silicon bipolar IC process and is available in an 8-lead MSOP package. The operating temperature range is −40°C to +85°C.

The ADF7023-J is a very low power, high performance, highly integrated 2FSK/GFSK/MSK/GMSK transceiver designed for operation in the 902 MHz to 958 MHz frequency band, which covers the ARIB Standard T96 band at 950 MHz. Data rates from 1 kbps to 300 kbps are supported.The transmit RF synthesizer contains a VCO and a low noise fractional-N phase locked loop (PLL) with an output channel frequency resolution of 400 Hz. The VCO operates at twice the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from −20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allow for Tx antenna diversity.The receiver is exceptionally linear, achieving an IP3 specification of −12.2 dBm and −11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at a ±2 MHz offset and 74 dB at a ±10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, AFC loop, allowing the PLL to find and correct any RF frequency errors in the recovered packet. A patent pending image rejection calibration scheme is available by downloading the image rejection calibration firmware module to program RAM. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.See data sheet for additional information.Applications Smart metering IEEE 802.15.4g Home automation Process and building control Home Energy Management Systems (HEMS) Wireless sensor networks (WSNs) Wireless healthcare

The AD9364 is a 1 x 1 channel high performance, highly integrated RF Agile Transceiver™. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9364 operates in the 70 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.The AD9364 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).Applications Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL± pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL± pins are used to stop this operation.The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS.The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearizationPRODUCT HIGHLIGHTS High Performance ADC Core. Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. Low Power. Consumes only 695 mW at 500 MSPS. Ease of Use. On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface supports configuration of the device and customization for the user’s needs. 1.9 V or 3.3 V SPI and Serial Data Port Operation.

The ADF4152HV is a 5.0 GHz, fractional-N or integer N frequency synthesizer with an integrated high voltage charge pump. The synthesizer can drive external wideband voltage controlled oscillators (VCOs) directly, eliminating the need for operational amplifiers to achieve higher tuning voltages. The integrated high voltage charge pump simplifies design and reduces cost while improving phase noise, in contrast to active filter topologies, which tend to degrade phase noise compared to passive filter topologies.The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin and software controllable.A simple 3-wire interface controls all on-chip registers. The charge pump operates from a power supply ranging from 6.0 V to 30 V, whereas the rest of the device operates from 3.0 V to 3.6 V. The ADF4152HV can be powered down when not in use.Applications Wireless infrastructure Microwave point to point/point to multipoint radios Very small aperture terminal (VSAT) radios Test equipment Private land mobile radios

The LTC6430-20 is a differential gain block amplifier designed to drive high resolution, high speed ADCs with excellent linearity beyond 1000MHz and with low associated output noise. The LTC6430-20 operates from a single 5V power supply and consumes only 850mW.In its differential configuration, the LTC6430-20 can directly drive the differential inputs of an ADC. Using 1:2 baluns, the device makes an excellent 50Ω wideband balanced amplifier. While using 1:1.33 baluns, the device creates a high fidelity 40MHz to 1000MHz 75Ω CATV amplifier.The LTC6430-20 is designed for ease of use, requiring a minimum of support components. The device is internally matched to 100Ω differential source/load impedance. On-chip bias and temperature compensation ensure consistent performance over environmental changes.The LTC6430-20 uses a high performance SiGe BiCMOS process for excellent repeatability compared with similar GaAs amplifiers. All A-grade LTC6430-20 devices are tested and guaranteed for OIP3 at 380MHz. The LTC6430-20 is housed in a 4mm × 4mm, 24-lead, QFN package with an exposed pad for thermal management and low inductance. A single-ended 50Ω IF gain block with similar performance is also available, see the related LTC6431-20.Applications Differential ADC Driver Differential IF Amplifier OFDM Signal Chain Amplifier 50Ω Balanced IF Amplifier 75Ω CATV Amplifier 700MHz to 800MHz LTE Amplifier Low Phase Noise Clock or LO Amplifier