The HMC596LP4(E) is a low-cost 4x2 switch matrix in a leadless QFN 4x4 mm surface mount package for use in Satellite/DBS, LNBs and multiswitches from 200 to 3000 MHz. A positive voltage controlled 4 bit decoder is integrated on the switch. The switches may be used in either 75 ohm or 50 ohm systems.Both switch outputs (OP1 & OP2) can independently select any of the four inputs (HH, HL, VH, VL) or simultaneously select the same inputs. Note that the switch is bi-directional and input/output functionality may be interchanged. All data presented was measured in a 50 ohm (input/output) system.APPLICATIONS DBS LNBs & Multiswitches Cable Modem/CATV Cellular Systems

The HMC326MS8G & HMC326MS8GE are high efficiency GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC driver amplifiers which operate between 3.0 and 4.5 GHz. The amplifier is packaged in a low cost, surface mount 8 leaded package with an exposed base for improved RF and thermal performance. The amplifier provides 21 dBof gain and +26 dBm of saturated power from a +5V supply voltage. Power down capability is available to conserve current consumption when the amplifier is not in use. Internal circuit matching was optimized to provide greater than 40% PAE.Applications Microwave Radios Broadband Radio Systems Wireless Local Loop Driver Amplifier

The HMC414MS8G(E) is a high efficiency GaAs InGaP Heterojunction Bipolar Transistor (HBT) MMIC Power amplifier which operates between 2.2 and 2.8 GHz. The amplifier is packaged in a low cost, surface mount 8 leaded package with an exposed base for improved RF and thermal performance. With a minimum of external components, the amplifier provides 20 dB of gain, +30 dBm of saturated power at 32% PAE from a +5V supply voltage. The amplifier can also operate with a 3.6V supply. Vpd can be used for full power down or RF output power/ current control.Applications BLUETOOTH MMDS

The HMC437MS8G(E) is a low noise Divide-by-3 Static Divider utilizing InGaP GaAs HBT technology in a low cost 8 lead surface mount plastic package. This device operates from DC (with a square wave input) to 7 GHz input frequency from a single +5V DC supply. The low additive SSB phase noise of -153 dBc/Hz at 100 kHz offset helps the user maintain good system noise performance.APPLICATIONS UNII, Point-to-Point & VSAT Radios 802.11a & HiperLAN WLAN Fiber Optic Cellular/3G Infrastructure

The HMC375LP3(E) is a high dynamic range GaAs PHEMT MMIC Low Noise Amplifier are ideal for GSM & CDMA cellular basestation front- end receivers operating between 1.7 and 2.2 GHz. This LNA has been optimized to provide 0.9 dB noise figure, 17 dB gain and +33 dBm output IP3 from a single supply of +5V @ 136mA. Input and output return losses are 14 dB typical with the LNA requiring minimal external components to optimize the RF input match, RF ground and DC bias.Applications GSM, GPRS & EDGE CDMA & W-CDMA DECT

The HMC822LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an Integrated Voltage Controlled Oscillator (VCO). The synthesizer consists of an integrated low noise VCO with a triband output, an autocalibration subsystem for low voltage VCO tuning, a very low noise digital Phase Detector (PD), a precision controlled charge pump, a low noise reference path divider and a fractional divider.The fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fine step sizes and low spurious products. The phase detector (PD) features cycle slip prevention (CSP) technology to allow faster frequency hopping times. Ultra low in-close phase noise and low spurious also allows wider loop bandwidths for faster frequency hopping and low micro-phonics.For theory of operation and register map refer to the 'PLLs with Integrated VCO - RF VCOs' Operating Guide.Applications Cellular/4G Infrastructure Repeaters and Femtocells Communications Test Equipment CATV Equipment Phased Array Applications DDS Replacement? Very High Data Rate Radios

The HMC942LP4E is a x2 active broadband frequency multiplier utilizing GaAs pHEMT technology in a leadless RoHS compliant SMT package. When driven by a +4 dBm signal, the multiplier provides +17 dBm typical output power from 13 to 24.6 GHz. The Fo and 3Fo isolations are >20 dBc at 19 GHz. The HMC942LP4E is ideal for use in LO multiplier chains for Pt-to-Pt & VSAT Radios yielding reduced parts count vs. traditional approaches.APPLICATIONS Clock Generation Applications: SONET OC-192 & SDH STM-64 Point-to-Point & VSAT Radios Test Instrumentation Military & Space Sensors

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz.?The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package.?The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.?Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution.?Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution.?With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures.?Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.?Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF?, SYNCINB?AB, and SYNCINB?CD input pins.?The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI.?The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the ?40?C to +105?C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers?3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios

The AD8361 is a mean-responding power detector for use inhigh frequency receiver and transmitter signal chains, up to2.5 GHz. It is very easy to apply. It requires a single supply onlybetween 2.7 V and 5.5 V, a power supply decoupling capacitor,and an input coupling capacitor in most applications. Theoutput is a linear-responding dc voltage with a conversion gainof 7.5 V/V rms. An external filter capacitor can be added toincrease the averaging time constant.The AD8361 is intended for true power measurement of simpleand complex waveforms. The device is particularly useful formeasuring high crest-factor (high peak-to-rms ratio) signals,such as CDMA and W-CDMA.The AD8361 has three operating modes to accommodate avariety of analog-to-digital converter requirements: Ground reference mode, in which the origin is zero. Internal reference mode, which offsets the output 350 mV above ground. Supply reference mode, which offsets the output to VS/7.5.The AD8361 is specified for operation from ?40?C to +85?Cand is available in 8-lead MSOP and 6-lead SOT-23 packages. Itis fabricated on a proprietary high fT silicon bipolar process.

The HMC6787ALC5A is a compact GaAs MMIC I/Q variable gain upconverter in a leadless RoHS compliant SMT package. This device provides a small signal conversion gain of 11 dB with 17 dBc of sideband rejection, and 13 dB of gain control. The HMC6787ALC5A utilizes a RF variable gain amplifier preceded by an I/Q mixer where the LO is driven by a X2 multiplier. IF1 and IF2 mixer inputs are provided and an external 90? hybrid is needed to select the required sideband. The I/Q mixer topology reduces the need for filtering of the unwanted sideband. The HMC6787ALC5A is a much smaller alternative to hybrid style single sideband upconverter assemblies and it eliminates the need for wire bonding by allowing the use of surface mount manufacturing techniques.APPLICATIONS Point-to-Point and Point-to-Multi-Point Radio Military Radar, EW & ELINT Satellite Communications Sensors