Phase Locked Loops - PLL PLL + VCO 50-3000MHz

Modulator/Demodulator SMT Direct I/Q Modulator, 450 - 4000 MHz

RF Mixer GaAs Sub Harmonic Mix Chip, 26 - 33 GHz

RF Amplifier lo Noise amp SMT, 1.7 - 2.2 GHz

RF Amplifier Driver amp Chip, 5 - 20 GHz

Prescaler InGaP HBT Divide-By-2 Chip, DC - 11 GHz

RF Amplifier WBand lo Phase Noise amp SMT, 2 - 18 GHz

The AD9364 is a 1 x 1 channel high performance, highly integrated RF Agile Transceiver™. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9364 operates in the 70 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.The AD9364 is packaged in a 10 mm × 10 mm, 144-ball chip scale package ball grid array (CSP_BGA).Applications Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL± pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL± pins are used to stop this operation.The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS.The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.APPLICATIONS Wireless and wired broadband communications Communications test equipment Power amplifier linearizationPRODUCT HIGHLIGHTS High Performance ADC Core. Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input. Low Power. Consumes only 695 mW at 500 MSPS. Ease of Use. On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design. Serial Port Control. Standard serial port interface supports configuration of the device and customization for the user’s needs. 1.9 V or 3.3 V SPI and Serial Data Port Operation.

The AD8313 is a complete multistage demodulating logarithmic amplifier that can accurately convert an RF signal at its input to an equivalent decibel-scaled value at its dc output. The AD8313 maintains a high degree of log conformance for signal frequencies from 0.1 GHz to 2.5 GHz. Application is straightforward, requiring only a single supply of 2.7 V to 5.5 V and the addition of a suitable input and supply decoupling. Operating on a 3 V supply, its 13.7 mA consumption (for TA = 25°C) is only 41 mW. A power-down feature is provided; the input is taken high to initiate a low current (20 µA) sleep mode, with a threshold at half the supply voltageThe AD8313 is fabricated on Analog Devices, Inc., advanced 25 GHz silicon bipolar IC process and is available in an 8-lead MSOP package. The operating temperature range is −40°C to +85°C.