The AD8349 is high performance quadrature modulator design for use as a single stage up-converter within wireless infrastructure equipment.The AD8349 provides a high output power and very low noise floor supporting a significant improvement in the output signal range. Additionally the excellent phase and amplitude balance accuracy support a higher sideband suppression specification enabling higher order / capacity QAM modulated radios.The AD8349 has been tested for use over the common Cellular bands (900 MHz, 1.9 GHz, 2.1 GHz) meeting the needs as specified by the CDMA/GSM Edge/W-CDMA standards.The AD8349 is supplied in 16-lead Thin Shrunk Small Outline (TSSOP) package, and fully specified over -40ºC to 85ºC temperature range.APPLICATIONS Cellular/PCS communication systems infrastructure WCDMA/CDMA2000/PCS/GSM/EDGE Wireless LAN/wireless local loop LMDS/broadband wireless access systemsAVAILABILITYSamples (part number AD8349ARE) and an evaluation board (part number AD8349-EVAL) are available. Other Modulator / Demodulator ProductsAD8345 - 250 - 1000 MHz RF / IF Quadrature ModulatorAD8346 - 2.5 GHz Direct Conversion Quadrature ModulatorAD8347 - 800 MHz to 2.7 GHz RF / IF Quadrature DemodulatorAD8348 - 50 - 1000 MHz RF / IF Quadrature Demodulator

The ADG901/ADG902 are wideband switches that use a complementary metal-oxide semiconductor (CMOS) process to provide high isolation and low insertion loss to 1 GHz. The ADG901 is an absorptive (matched) switch with 50 Ω terminated shunt legs, while the ADG902 is a reflective switch. These devices are designed such that the isolation is high over the dc to 1 GHz frequency range. These switches enable the user to pass dc signals up to 0.5 V without the use of a dc blocking capacitor. They have on-board CMOS control logic, thus eliminating the need for external controlling circuitry. The control inputs are both CMOS and LVTTL compatible. The low power consumption of these CMOS devices makes them ideally suited to wireless applications and general-purpose high frequency switching.Product Highlights 40 dB Off Isolation at 1 GHz 0.8 dB Insertion Loss at 1 GHz 17 dBm P1dB at 1 GHzApplications Wireless communications General purpose RF switching Dual-band applications High speed filter selection Digital transceiver front-end switch IF switching Tuner modules Antenna diversity switching list

The AD8285 is designed for low cost, low power, compact size, flexibility, and ease of use. It contains four channels of a low noise preamplifier (LNA) with a programmable gain amplifier (PGA) and an antialiasing filter (AAF) plus one direct-to-ADC channel, all integrated with a single 12-bit analog-to-digital converter (ADC).Each channel features a gain range of 16 dB to 34 dB in 6 dB increments and an ADC with a conversion rate of up to 72 MSPS. The combined input referred noise voltage of the entire channel is 3.5 nV/√Hz at maximum gain. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.Fabricated in an advanced complementary metal oxide semiconductor (CMOS) process, the AD8285 is available in a 10 mm × 10 mm, RoHS compliant, 72-lead LFCSP that is specified over the automotive temperature range of −40°C to +105°C.APPLICATIONS Automotive radar Adaptive cruise control Collision avoidance Blind spot detection Self parking Electronic bumper

The AD9363 is a high performance, highly integrated RF agiletransceiver designed for use in 3G and 4G femtocell applications.Its programmability and wideband capability make it ideal for abroad range of transceiver applications. The device combines anRF front end with a flexible mixed-signal baseband section andintegrated frequency synthesizers, simplifying design-in byproviding a configurable digital interface to a processor. TheAD9363 operates in the 325 MHz to 3.8 GHz range, coveringmost licensed and unlicensed bands. Channel bandwidths fromless than 200 kHz to 20 MHz are supported.The two independent direct conversion receivers have state-of-the-artnoise figure and linearity. Each Rx subsystem includesindependent automatic gain control (AGC), dc offset correction,quadrature correction, and digital filtering, thereby eliminatingthe need for these functions in the digital baseband. The AD9363also has flexible manual gain modes that can be externallycontrolled. Two high dynamic range ADCs per channel digitizethe received I and Q signals and pass them through configurabledecimation filters and 128-tap finite impulse response (FIR)filters to produce a 12-bit output signal at the appropriatesample rate.The transmitters use a direct conversion architecture that achieveshigh modulation accuracy with ultralow noise. This transmitterdesign produces a best-in-class Tx EVM of −34 dB, allowingsignificant system margin for the external power amplifier (PA)selection. The on-board Tx power monitor can be used as apower detector, enabling highly accurate Tx powermeasurements.The fully integrated phase-locked loops (PLLs) provide lowpower fractional N frequency synthesis for all receive andtransmit channels. Channel isolation, demanded by FDDsystems, is integrated into the design. All voltage controlledoscillators (VCOs) and loop filter components are integrated.The core of the AD9363 can be powered directly from a 1.3 Vregulator. The IC is controlled via a standard 4-wire serial portand four real-time I/O control pins. Comprehensive power-downmodes are included to minimize power consumption duringnormal use. The AD9363 is packaged in a 10 mm × 10 mm,144-ball chip scale package ball grid array (CSP_BGA).Applications 3G enterprise femtocell base stations 4G femtocell base stations Wireless video transmission

The AD9371 is a highly integrated, wideband RF transceiveroffering dual channel transmitters and receivers, integrated synthesizers, and digital signal processing functions. The ICdelivers a versatile combination of high performance and low power consumption required by 3G/4G micro and macro BTSequipment in both FDD and TDD applications. The AD9371operates from 300 MHz to 6000 MHz, covering most of the licensed and unlicensed cellular bands. The IC supports receiver bandwidths up to 100 MHz. It also supports observation receiver and transmit synthesis bandwidths up to 250 MHz to accommodate digital correction algorithms.The transceiver consists of wideband direct conversion signalpaths with state-of-the-art noise figure and linearity. Each complete receiver and transmitter subsystem includes dc offset correction, quadrature error correction (QEC), and programmable digitalfilters, eliminating the need for these functions in the digitalbaseband. Several auxiliary functions such as an auxiliary analog-to-digital converter (ADC), auxiliary digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) are integratedto provide additional monitoring and control capability.An observation receiver channel with two inputs is included to monitor each transmitter output and implement interference mitigation and calibration applications. This channel also connects to three sniffer receiver inputs that can monitor radio activity in different bands.The high speed JESD204B interface supports lane rates up to 6144 Mbps. Four lanes are dedicated to the transmitters and four lanes are dedicated to the receiver and observation receiver channels.The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N frequency synthesis forthe transmitter, the receiver, the observation receiver, and theclock sections. Careful design and layout techniques provide theisolation demanded in high performance base station applications.All voltage controlled oscillator (VCO) and loop filter components are integrated to minimize the external component count. A 1.3 V supply is required to power the core of the AD9371, anda standard 4-wire serial port controls it. Other voltage supplies provide proper digital interface levels and optimize transmitterand auxiliary converter performance. The AD9371 is packaged in a12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).Applications 3G/4G micro and macro base stations (BTS) 3G/4G multicarrier picocells  FDD and TDD active antenna systems  Microwave, nonline of sight (NLOS) backhaul systems

The ADF7030-1 is a fully integrated, radio transceiver achieving high performance at very low power. The ADF7030-1 is ideally suited for applications that require long range, network robustness, and long battery life. It is suitable for applications that operate in the ISM, SRD, and licensed frequency bands at 169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz to 960 MHz. It provides extensive support for standards-based protocols like IEEE802.15.4g while also providing flexibility to support a wide range of proprietary protocols.The highly configurable low intermediate frequency (IF) receiver supports a large range of receiver channel bandwidths from 2.6 kHz to 406 kHz. This range of receiver channel bandwidths allows the ADF7030-1 to support ultranarrow-band, narrow-band, and wideband channel spacing.The ADF7030-1 features two independent PAs supporting output power ranges of −20 dBm to +13 dBm and −20 dBm to +17 dBm. The PAs support ultrafine adjustment of the power with a step resolution of 0.1 dB. The PA output power is exceptionally robust over temperature and voltage. The PAs have an automatic power ramp control to limit spectral splatter to meet regulatory standards.The ADF7030-1 features an on-chip ARM® Cortex®-M0 processor that performs radio control, radio calibration, and packet management. Cortex-M0 eases the processing burden of the host processor because the ADF7030-1 integrates the lower layers of a typical communication protocol stack. This internal processor also permits the download and execution of Analog Devices, Inc., provided firmware modules that can extend the functionality of the ADF7030-1.The ADF7030-1 has two packet modes: generic packet mode and IEEE802.15.4g mode. In generic packet mode, the packet format is highly flexible and fully programmable, thereby ensuring its compatibility with proprietary packet formats. In IEEE802.15.4g packet mode, the packet format conforms to the IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard, is also supported.The ADF7030-1 operates with a power supply range of 2.2 V to 3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems. An ultralow power deep sleep mode achieves a typical current of 10 nA with the configuration memory retained.A complete wireless solution can be built using a small number of external discrete components and a host processor (typically a microcontroller). The host processor can configure the ADF7030-1 using a simple command-based protocol over a standard 4-wire SPI interface. A single-byte command transitions the radio between states or performs a radio function.The ADF7030-1 is available in two package types: a 6 mm × 6 mm, 40-lead LFCSP and a 7 mm × 7 mm, 48-lead LQFP. Both package types use NiPdAu plating to mitigate against silver migration in high humidity applications. The ADF7030-1 operating temperature range is −40°C to +85°C.For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60, Figure 61, and Figure 75 in the Typical Performance Characteristics section, PA_COARSE is a programmable value that provides a coarse adjustment of the PA output power. This value can be programmed in the range of 1 to 6 for PA1, and from 1 to 10 for PA2. PA_FINE is a programmable value that provides a fine adjustment of the PA output power. This value can be programmed in the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a programmable value that provides a microadjustment (typically <0.1 dB) of the PA output power. This value can be programmed in the range of 1 to 31 for both PA1 and PA2. PAOLDO_VOUT_CON is a programmable value that configures the internal LDO voltage that provides bias for the PA. For additional information on these bit settings, see the ADF7030-1 Software Reference Manual, which is the detailed programming guide for the device.Applications IEEE 802.15.4g (MR-FSK PHY)  Wireless M-Bus (EN 13757-4) Smart metering Security and building automation  Active tag asset tracking Industrial control Wireless sensor networks (WSNs)

The LTC6431-15 is a gain-block amplifier with excellent linearity at frequencies beyond 1000MHz and with low associated output noise.The unique combination of high linearity, low noise and low power dissipation make this an ideal candidate for many signal-chain applications. The LTC6431-15 is easy to use, requiring a minimum of external components. It is internally input/output matched to 50Ω and it draws only 90mA from a single 5V supply.On-chip bias and temperature compensation maintain performance over environmental changes.The LTC6431-15 uses a high performance SiGe BiCMOS process for excellent repeatability compared with similar GaAs amplifiers. All A-grade LTC6431-15 devices are tested and guaranteed for OIP3 at 240MHz. The LTC6431-15 is housed in a 4mm x 4mm 24-lead QFN package with an exposed pad for thermal management and low inductance.Applications Single-Ended IF Amplifier ADC Driver CATV

The LTM9013 is a 300MHz wideband, low IF receiver. Utilizing an integrated system in a package (SiP) technology, it is a μModule® (micromodule) receiver that includes a dual high speed 14-bit A/D converter, lowpass filter, differential gain stages and a quadrature demodulator.The LTM9013 is perfect for wideband I/Q receiver applications, with AC performance that includes 59dB SNR and 1.3dB frequency flatness from DC to 300MHz. A highpass filter or simple AC coupling are used external to the device for design flexiblity. The integrated on-chip broadband transformers provide a 50Ω single-ended interface at the RF input.A 5V supply powers the demodulator and a 3.3V supply powers the IF amplifiers for minimal distortion. A 1.8V supply allows low power ADC operation. A separate output supply allows the DDR LVDS outputs to drive 1.8V logic. An optional multiplexer allows both channels to share a digital output bus. An optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.Applications Telecommunications Wideband, Low IF Receivers Digital Predistortion Receivers Cellular Base Stations

The SC2200 belongs to the 4th-generation family of RF PA linearizers (RFPAL) that provides increased integration and functionality over the previous generations. The device is a dual-path linearizer that is a fully-adaptive, RFIN/RFOUT predistortion linearization solution optimized for a wide range of amplifiers, power levels, and communication protocols. It supports 2G to 4G standards (FDD and TDD) from 698MHz to 2700MHz as well as an expanded range of signal bandwidths from 60MHz down to 1.2MHz. The SC2200 accepts single-ended RF signals to eliminate baluns and features a mirrored pinout facilitating design of both paths. The device uses the PA output and input signals to adaptively generate an optimized correction function to minimize the PA’s distortion. Using RF-domain analog signal processing enables the SC2200 to operate over wide bandwidths and with very low power consumption. The dual linearizer is optimized for high-performance MIMO applications, including small cells, active antenna, and distributed antenna systems.SC2200 and SC1894 RF Power Amplifier Linearizers RF Power Amplifier Linearization Technology ApplicationsAmplifier: Class A/AB, DohertyAverage PA Output Power Examples: Cellular Infrastructure: 27dBm to 40dBmBTS Amplifiers, RRH, Booster Amplifiers, Repeaters, Small Cells, Microcells, Picocells, DAS, AAS and MIMO SystemsCellular InfrastructurePA Process: LDMOS, GaN, HBT, GaAs and InGaPSingle/Multicarrier, Multistandard: CDMA/EVDO, TD-SCDMA, WiMAX, WCDMA/HSDPA, LTE, and TD-LTEWide Range of PAs and Output Power

The AD6649 is a mixed-signal intermediate frequency (IF) receiverconsisting of dual 14-bit, 250 MSPS ADCs and a wideband digitaldownconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.The dual ADC core features a multistage, differential pipelinedarchitecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digitaldownconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.The AD6649 receiver digitizes a wide spectrum of IF frequencies.Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.Flexible power-down options allow significant power savings,when desired.Programming for setup and control is accomplished using a 3-pinSPI-compatible serial interface.The AD6649 is available in a 64-lead LFCSP and is specified overthe industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE General-purpose software radios Broadband data applicationsPRODUCT HIGHLIGHTS Integrated dual, 14-bit, 250 MSPS ADC. Integrated wideband decimation filter and 32-bit complex NCO. Fast overrange and threshold detect. Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz. SYNC input allows synchronization of multiple devices. 3-pin, 1.8V SPI port for register programming and register readback.