Low Noise, 0.5% Tolerance, 5MHz to 28MHz, Pin Configurable Filter/ADC Driver Features: Pin Configurable Gain and Filter Response Up to 28MHz Few External Components Required Resistors Trimmed to 0.5% Typical Capacitors Trimmed to 0.5% Typical Very Low Noise: 80dB S/N in 100MHz Bandwidth Very Low Distortion (2VP-P): 1MHz: –100dBc 2nd, –123dBc 3rd 10MHz: –72dBc 2nd, –103dBc 3rd Adjustable Output Common Mode Voltage Rail-to-Rail Output Swing Power Configurability and Low Power Shutdown Tiny 0.75mm 20-Lead (4mm × 4mm) QFN Package

Full-Featured LED Driver with 1.5A Switch Current Features: 5000:1 True Color PWM™ Dimming Ratio 1.5A, 45V Internal Switch 100mV High Side Current Sense Open LED Protection Adjustable Frequency: 250kHz to 2.5MHz Wide Input Voltage Range: Operation from 3V to 30V Transient Protection to 40V Operates in Boost, Buck Mode and Buck-Boost Mode Gate Driver for PMOS LED Disconnect Constant-Current and Constant-Voltage Regulation CTRL Pin Provides 10:1 Analog Dimming Low Shutdown Current: <1μA Available in (4mm × 4mm) 16-Lead QFN and 16-Pin TSSOP Packages

Ultralow EMI 28VIN, 6A DC/DC Module Regulator Features: Complete Low EMI Switch Mode Power Supply Wide Input Voltage Range: 4.5V to 28V 6A DC Typical, 8A Peak Output Current 0.6V to 5V Output Voltage Range EN55022 Class B Certified Output Voltage Tracking and Margining PLL Frequency Synchronization ±1.75% Total DC Error Power Good Output Current Foldback Protection (Disabled at Start-Up) Parallel/Current Sharing Current Mode Control Up to 93% Efficiency at 5VIN, 3.3VOUT Programmable Soft-Start Output Overvoltage Protection –55°C to 125°C Operating Temperature Range (LTM4606MP) SnPb or RoHS Compliant Finish 15mm × 15mm × 2.82mm LGA Package 15mm × 15mm × 3.42mm BGA Package

Secondary-Side Synchronous Forward Controller Features: Secondary-Side Control for Fast Transient Response Self-Starting Architecture Eliminates Need for Separate Bias Regulator Proprietary Gate Drive Encoding Scheme Reduces System Complexity Current Mode Control Ensures Current Sharing PLL Fixed Frequency: 100kHz to 500kHz ±1% Output Voltage Accuracy OPTI-LOOP Compensation Available in a Narrow 16-Lead SSOP Package

Single Switch Synchronous Forward Controller Features: Synchronous Rectifier Control for High Efficiency Programmable Volt-Second Clamp Output Power Levels from 25W to 500W Low Current Start-Up (LT1952: 460µA; VIN On/Off = 14.25V/8.75V) (LT1952-1: 400µA; VIN On/Off = 7.75V/6.5V) True PWM Soft-Start Low Stress Short Circuit Protection Precision 107mV Current Limit Threshold Adjustable Delay for Synchronous Timing Accurate Shutdown Threshold with Programmable Hysteresis Programmable Slope Compensation Programmable Leading Edge Blanking Programmable Frequency (100kHz to 500kHz) Synchronizable to an External Clock up to 1.5 • fOSC Internal 1.23V Reference 2.5V External Reference Current Mode Control Small 16-Pin SSOP Package

Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Features: Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock See data sheet for additional features

Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors Features:Pin-programmable output rateOutput data rate: 10 Hz, 50 Hz, 60 Hz, 120 HzPin-programmable PGAGain: 1, 8, 64, 128Pin-programmable power-down and resetRMS noise: 15 nV @ 10 Hz (gain = 128)Up to 21.5 noise free bits (gain = 1)Please see data sheet for additional features

Dual, 16-Bit, 2.8 GSPS, TxDAC+ Digital-to-Analog Converter Features: Support input data rate >2 GSPS Proprietary low spurious and distortion design SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, or 8× interpolation filter Low power architecture Transmit enable function allows extra power saving and instant control of the output status High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.42 W at 1.6 GSPS full operating conditions 88-lead LFCSP with exposed pad

Quad, 16-Bit, 2.4 GSPS, TxDAC+ Digital-to-Analog Converter Features: Supports input data rates up to 1 GSPS Proprietary, low spurious and distortion design Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at 180 MHz IF Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at 180 MHz IF SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone Flexible 8-lane JESD204B interface Multiple chip synchronization Fixed latency Data generator latency compensation Input signal power detection High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Digital quadrature modulation using a numerically controlled oscillator (NCO) Nyquist band selection—mix mode Selectable 1×, 2×, 4×, and 8× interpolation filters Low power: 2.11 W at 1.6 GSPS, full operating conditions 88-lead, exposed pad LFCSP

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch