Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 600MHz (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Dual-core SHARC+ DSP (w/768KB L1), 1MB Shared L2, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature range Memory Large on-chip L2 SRAM with ECC protection, up to 1 MBAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

Single-core SHARC+ (w/384KB L1), arm Cortex-A5, 1MB Shared L2, 10/100 Ethernet, 176-LQFP Features: Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed arm® Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm 400-ball CSP_BGA and 176-lead LQFP_EP, RoHS compliant Low system power across automotive temperature rangeMemory Large on-chip L2 SRAM with ECC protection, up to 1 MB One L3 interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.5 V capable DDR3L devices), DDR2, or LPDDR1 SDRAM devicesAdditional Features Security and Protection Cryptographic hardware accelerators Fast secure boot with IP protection Support for arm® TrustZone Accelerators FIR, IIR offload engines Qualified for automotive applications

Dual-core SHARC+ and ARM Cortex-A5 SOC, dual DDR, 2xEthernet, 2xUSB, SDIO, PCIe, 529-cspBGA Features: 500 MHz (3.0 GFLOPS) per core 5Mbits/640KB L1 memory/core with parity Optional cache/SRAM mode 32-bit, 40-bit & 64-bit floating point supportARM Core Infrastructure: 500 MHz ARM Cortex-A5 (with Neon/FPU) 32kByte/32kByte L1 Instr./Data Cache 256kByte L2 CacheShared System Memory 256KB L2 SRAM with ECC protectionUp to Two High Speed Memory Controllers DDR3-900, DDR2-800 & LPDDR (16-bit)Advanced Hardware Accelerators FFT/iFFT (20 GFLOPS, 5usec per 1K-pt FFT) FIR/IIR and SINC Filters, ASRC Security Crypto Engines with OTPPackaging 19mm x 19mm BGA  (0.8mm pitch) Commercial, Industrial & Automotive 2x Ethernet MAC One Gigabit (RGMII) and one 10/100 (RMII) With IEEE-1588 & AVB support (QoS & clock recovery) 2x USB2.0 HS OTG/Device Controllers (MAC/PHY) 2x CAN2.0 SD/SDIO/MMC/eMMC (with SDXC support) PCIe2.0 (1 lane) (SC589 only) Up to 8 Full SPORT interfaces (w/ TDM & I2S modes) S/PDIF Tx/Rx, 8x ASRC pairs, PCG  2x Dual-SPI and 1x QuadSPI (w/ direct  execution) 3x I2C and 3x UARTs (w/ Flow Control) Enhanced Parallel Peripheral Interface For video I/O or parallel converter interface 2x Link Ports (bi-directional, 8-bit, up to 150MB/sec) 3x Enhanced PWM,  ADC Control Module (ACM) 8x GP Timer, 1x GP Counter, WDT and RTC Up to 102 GPIO (mux’ed w/ other interfaces) 8-ch 12-bit 1MSPS Housekeeping ADC Thermal Sensor

Low Cost JFET Input Operational Amplifier Features: TL082/TL084 compatible Low input bias current: 10 pA maximum Offset voltage 5.5 mV maximum (ADTL082A/ADTL084A) 9 mV maximum (ADTL082J/ADTL084J) ±15 V operation Low noise: 16 nV/√Hz Wide bandwidth: 5 MHz Slew rate: 20 V/μs CMRR: 80 dB minimum Total harmonic distortion: 0.001% Supply current: 1.2 mA typical Unity-gain stable

Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Features: EEMBC ULPMark™-CP score (3 V): 189 Ultra low power active and hibernate modes Active mode dynamic current: 41 μA/MHz (typical) Flexi mode: 400 μA (typical) Hibernate mode: 0.65 μA (typical) Shutdown mode: 50 nA (typical) Shutdown mode (fast wake-up): 0.20 μA (typical) ARM Cortex-M4F processor at 52 MHz with FPU, MPU, ITM with SWD interface Power management Single-supply operation (connected to VBAT pins): 1.74 V to 3.6 V Optional buck converter for improved efficiency Memory options 512 kB of embedded flash memory with ECC 4 kB of cache memory to reduce active power 128 kB of configurable system SRAM with parity Safety Watchdog with dedicated on-chip oscillator Hardware CRC with programmable polynomial Multiparity bit protected SRAM ECC protected embedded flash Security Hardware cryptographic accelerator supporting AES-128, AES-256, and SHA-256 Protected key storage in flash, SHA-256-based keyed HMAC and key wrap and unwrap User code protection TRNG Digital peripherals 3 SPI interfaces to enable glueless interface to sensors, radios, and converters 1 I2C and 2 UART peripheral interfaces SPORT for natively interfacing with converters and radios Programmable GPIOs (44 in LFCSP and 51 in WLCSP) 3 general-purpose timers with PWM support RGB timer for driving RGB LED RTC0 for time keeping RTC1 with SensorStrobe and time stamping Programmable beeper 27-channel DMA controller Clocking features 26 MHz clock: on-chip oscillator, external crystal oscillator, SYS_CLKIN for external clock, and integrated PLL 32 kHz clock: on-chip oscillator and low power crystal oscillator Clock fail detection for external crystals Analog peripherals 12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital comparator

Ultra Low Power ARM Cortex-M4F MCU with Integrated Power Management Features: EEMBC ULPMark™-CP score (3 V): 189 Ultra low power active and hibernate modes Active mode dynamic current: 41 μA/MHz (typical) Flexi mode: 400 μA (typical) Hibernate mode: 0.65 μA (typical) Shutdown mode: 50 nA (typical) Shutdown mode (fast wake-up): 0.20 μA (typical) ARM Cortex-M4F processor at 52 MHz with FPU, MPU, ITM with SWD interface Power management Single-supply operation (connected to VBAT pins): 1.74 V to 3.6 V Optional buck converter for improved efficiency Memory options 512 kB of embedded flash memory with ECC 4 kB of cache memory to reduce active power 128 kB of configurable system SRAM with parity Safety Watchdog with dedicated on-chip oscillator Hardware CRC with programmable polynomial Multiparity bit protected SRAM ECC protected embedded flash Security Hardware cryptographic accelerator supporting AES-128, AES-256, and SHA-256 Protected key storage in flash, SHA-256-based keyed HMAC and key wrap and unwrap User code protection TRNG Digital peripherals 3 SPI interfaces to enable glueless interface to sensors, radios, and converters 1 I2C and 2 UART peripheral interfaces SPORT for natively interfacing with converters and radios Programmable GPIOs (44 in LFCSP and 51 in WLCSP) 3 general-purpose timers with PWM support RGB timer for driving RGB LED RTC0 for time keeping RTC1 with SensorStrobe and time stamping Programmable beeper 27-channel DMA controller Clocking features 26 MHz clock: on-chip oscillator, external crystal oscillator, SYS_CLKIN for external clock, and integrated PLL 32 kHz clock: on-chip oscillator and low power crystal oscillator Clock fail detection for external crystals Analog peripherals 12-bit SAR ADC, 1.8 MSPS, 8 channels, and digital comparator

Precision Analog Microcontroller, 16-Bit Analog Input/Output with MDIO Interface, Arm Cortex-M33 Features: Analog input/output Multichannel, 16-bit, 2 MSPS ADC Up to 16 external channels On-chip die temperature monitor 4 power monitor channels 4 PGA/TIA channels supporting voltage and current measurements Fully differential and single-ended modes 0 V to VREF analog input range 12-bit voltage output DACs 8× 0 V to 2.5 V, 1 kΩ load 4× 0 V to 2.5 V, 2.5 kΩ load On-chip low drift voltage reference, 1.25 V or 2.5 V Buffered 1.25 V or 2.5 V output 4 voltage comparators Microcontroller 32-bit Arm Cortex-M33 core, 32-bit RISC architecture, FPU Serial wire port supports code download and debug Clocking options 16 MHz on-chip oscillator 160 MHz PLL output with programmable divider External clock source Memory 2× 512 kB independent Flash/EE memories 10,000-cycle Flash/EE endurance 20-year Flash/EE retention 128 kB SRAM with ECC Software triggered, in circuit reprogrammability via MDIO or I2C On-chip peripherals 2× UART, 3× SPI, 3× I2C serial input/output Multilevel voltage (3.3 V, 1.8 V, 1.2 V) GPIOs MDIO slave up to 10 MHz 5 general-purpose timers Wake-up timer (WUTs) Watchdog timers (WDTs) 32-element PLA 16-bit PWM 10 external Interrupts Power Multiple supplies: 3.3 V for voltage DACs and ADCs, and 3.3 V, 1.8 V, or 1.2 V for digital inputs/outputs Flexible operating modes for low power applications Packages and temperature range 5 mm × 5 mm 81-ball CSP_BGA and 3.46 mm × 3.46 mm 64-ball WLCSP BGA package uses ULA molding compounds Fully specified for −40°C to +105°C operation Tools Low cost quick start development system Full third-party support  

Precision Analog Microcontroller, 16-Bit Analog Input/Output with MDIO Interface, Arm Cortex-M33 Features: Analog input/output Multichannel, 16-bit, 2 MSPS ADC Up to 16 external channels On-chip die temperature monitor 4 power monitor channels 4 PGA/TIA channels supporting voltage and current measurements Fully differential and single-ended modes 0 V to VREF analog input range 12-bit voltage output DACs 8× 0 V to 2.5 V, 1 kΩ load 4× 0 V to 2.5 V, 2.5 kΩ load On-chip low drift voltage reference, 1.25 V or 2.5 V Buffered 1.25 V or 2.5 V output 4 voltage comparators Microcontroller 32-bit Arm Cortex-M33 core, 32-bit RISC architecture, FPU Serial wire port supports code download and debug Clocking options 16 MHz on-chip oscillator 160 MHz PLL output with programmable divider External clock source Memory 2× 512 kB independent Flash/EE memories 10,000-cycle Flash/EE endurance 20-year Flash/EE retention 128 kB SRAM with ECC Software triggered, in circuit reprogrammability via MDIO or I2C On-chip peripherals 2× UART, 3× SPI, 3× I2C serial input/output Multilevel voltage (3.3 V, 1.8 V, 1.2 V) GPIOs MDIO slave up to 10 MHz 5 general-purpose timers Wake-up timer (WUTs) Watchdog timers (WDTs) 32-element PLA 16-bit PWM 10 external Interrupts Power Multiple supplies: 3.3 V for voltage DACs and ADCs, and 3.3 V, 1.8 V, or 1.2 V for digital inputs/outputs Flexible operating modes for low power applications Packages and temperature range 5 mm × 5 mm 81-ball CSP_BGA and 3.46 mm × 3.46 mm 64-ball WLCSP BGA package uses ULA molding compounds Fully specified for −40°C to +105°C operation Tools Low cost quick start development system Full third-party support  

3.0 kV rms, Dual-Channel Digital Isolators Features: High common-mode transient immunity: 100 kV/µs typical High robustness to radiated and conducted noise Low propagation delay 13 ns maximum for 5 V operation 15 ns maximum for 1.8 V operation 150 Mbps minimum data rate Safety and regulatory approvals UL recognition: 3000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE certificate of conformity DIN VDE V 0884-11:2017-01 VIORM = 565 V peak CQC certification per GB4943.1-2011 Backward compatibility ADuM120N0 pin-compatible with ADuM1285 ADuM120N1 pin-compatible with ADuM1280 and ADuM1200 ADuM121N0 pin-compatible with ADuM1286 ADuM121N1 pin-compatible with ADuM1281 and ADuM1201 Low dynamic power consumption 1.8 V to 5 V level translation High temperature operation: 125°C Failsafe high or low options 8-lead, RoHS-compliant, SOIC package Qualified for automotive applications