Tiny 16-Bit SPI nanoDAC+, with 2 (16-Bit) LSB INL and 2 ppm/C Reference Features: Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP High relative accuracy (INL): ±2 LSB maximum at 16 bits AD5683R/AD5682R/AD5681R Low drift, 2.5 V reference: 2 ppm/°C typical Selectable span output: 2.5 V or 5 V Total unadjusted error (TUE): 0.06% of FSR maximum Offset error: ±1.5 mV maximum Gain error: ±0.05% of FSR maximum Low glitch: 0.1 nV-sec High drive capability: 20 mA Low power: 1.2 mW at 3.3 V Independent logic supply: 1.62 V logic compatible Wide operating temperature range: −40°C to +105°C Robust 4 kV HBM ESD protection

High Precision, Impedance & Electrochemical Front End Features: Analog input 16-bit ADC with both 800 kSPS and 1.6 MSPS options Voltage, current, and impedance measurement capability Internal and external current and voltage channels Ultralow leakage switch matrix and input mux Input buffers and programmable gain amplifier Voltage DACs Dual output voltage DAC with an output range of 0.2 V to 2.4 V 12-bit VBIAS0 output to bias potentiostat 6-bit VZERO0 output to bias TIA Ultra low power: 1 µA 1 high speed, 12-bit DAC Output range to sensor: ±607 mV Programmable gain amplifier on output with gain settings of 2 and 0.05 Amplifiers, accelerators, and references 1 low power, low noise potentiostat amplifier suitable for potentiostat bias in electrochemical sensing 1 low noise, low power TIA, suitable for measuring sensor current output 50 pA to 3 mA range Programmable load and gain resistors for sensor output Analog hardware accelerators Digital waveform generator Receive filters Complex impedance measurement (DFT) engine 1 high speed TIA to handle wide bandwidth input signals from 0.015 Hz up to 200 kHz Digital waveform generator for generation of sinusoid and trapezoid waveforms 2.5 V and 1.82 V internal reference voltage sources System level power savings Fast power-up and power-down analog blocks for duty cycling Programmable AFE sequencer to minimize workload of host controller 6 kB SRAM to preprogram AFE sequences Ultra low power potentiostat channel: 6.5 µAof current consumption when powered on and all other blocks in hibernate mode Smart sensor synchronization and data collection Cycle accurate control of sensor measurement Sequencer controlled GPIOs On-chip peripherals SPI serial input/output Wake-up timer Interrupt controller Power 2.8 V to 3.6 V supply 1.82 V input/output compliant Power-on reset Hibernate mode with low power DAC and potentiostat amplifier powered up to maintain sensor bias Package and temperature range 3.6 mm × 4.2 mm, 56-ball WLCSP 7 mm × 7 mm, 48-lead LFCSP Fully specified for operating temperature range of −40°C to +85°C AD5940 and AD5941 fully specified for operating temperature range of −40°C to +85°C AD5941W fully specified for operating temperature range of −40°C to +105°C AEC-Q100 qualified for automotive applications

24-Bit, 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Features: Fast and flexible output rate: 5 SPS to 250 kSPS Performance specifications 17.2 noise free bits at 250 kSPS 20.2 noise free bits at 2.5 kSPS 24 noise free bits at 20 SPS INL: ±1 ppm of FSR 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 8 fully differential channels or 16 single-ended channels Crosspoint multiplexer Channel scan data rate of 50 kSPS/channel (20 ìs settling) On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock Power supply: AVDD1 − AVSS = 5 V, AVDD2 = IOVDD = 2 V to 5 V (nominal) Split supply with AVDD1/AVSS at ±2.5 V ADC current: 8.4 mA Temperature range: −40°C to +105°C 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) Serial port interface (SPI), QSPI, MICROWIRE, and DSP compatible

1 MSPS, 12-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators Features: Dual simultaneous sampling 12-bit, 2-channel analog-to-digital converter (ADC) True differential analog inputs Programmable gain stage: ×1, ×2, ×3, ×4, ×6, ×8, ×12, ×16, ×24, ×32, ×48, ×64, ×96, ×128 Throughput rate per ADC 1 MSPS for AD7262 500 kSPS for AD7262-5 Analog input impedance: >1 GΩ Wide input bandwidth −3 dB bandwidth: 1.7 MHz at gain = 2 4 on-chip comparators SNR: 73 dB typical at gain = 2, 66 dB typical at gain = 32 Device offset calibration, system gain calibration On-chip reference: 2.5 V −40°C to +105°C operation High speed serial interface SPI/QSPI™/MICROWIRE/DSP compatible 48-lead LFCSP and LQFP

12-Bit Power Amplifier Current Controller with ADC, DACs, Temperature and Current Sensors Features: 4 closed-loop power amplifier (PA) drain current controllers Built-in PA protection, sequencing, and alert features Compatible with both depletion mode and enhancement mode power amplifiers Highly integrated 4 uncommitted 12-bit analog-to-digital converter (ADC) inputs ±0.5 LSB typical integral nonlinearity (INL) Eight 12-bit voltage digital-to-analog converters (DACs) 1.3 μs maximum settling 4 high-side current sense amplifiers, ±0.1% gain error 2 external temperature sensor inputs, ±1.1°C accuracy Internal temperature sensor, ±1.25°C accuracy 2.5 V on-chip reference Flexible monitoring and control ranges ADC input ranges: 0 V to 1.25 V, 0 V to 2.5 V, and 0 V to 5 V Bipolar DAC ranges: 0 V to +5 V, −4 V to +1 V, and −5 V to 0 V Bipolar DAC reset and clamping relative to VCLAMPx voltage Unipolar DAC ranges: 0 V to 5 V, 2.5 V to 7.5 V, and 5 V to 10 V Current sense gain: 6.25, 12.5, 25, 50, 100, and more Adjustable closed-loop setpoint ramp time High-side voltage current sensing 4 current sense inputs 4 V to AVSS + 60 V, ±200 mV input range Small package and flexible interface Serial port interface (SPI) with VDRIVE supporting 1.8 V, 3 V, and 5 V interfaces 56-lead LFCSP Temperature range: −40°C to +125°C

3V/5V, 1mW, 3-Channel Pseudo Differential, 16-Bit Sigma-Delta ADC Features: Three Pseudo Differential Input Channel ADCs 16 Bits No Missing Codes 0.003% Nonlinearity Programmable Gain Front End Gains from 1 to 128 Three-Wire Serial Interface SPI®, QSPI™, MICROWIRE™ and DSP Compatible Schmitt Trigger Input on SCLK See data sheet for additional features

3-Channel, Low Noise, Low Power, 16-Bit, Sigma Delta ADC with On-Chip In-Amp Features: RMSnoise:  27 nV at 4.17 Hz (AD7799)  65 nV at 16.7 Hz (AD7799)  40 nV at 4.17 Hz (AD7798)  85 nV at 16.7 Hz (AD7798) Current: 380 μA typical Power-down: 1 μA maximum Low noise, programmable gain, instrumentation amp Internal clock oscillator Simultaneous 50 Hz/60 Hz rejection Reference detect Low-side power switch Programmable digital outputs Burnout currents Power supply: 2.7 V to 5.25 V Update rate: 4.17 Hz to 470 Hz 3 differential inputs

18-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common-mode voltage range High common-mode rejection Single-ended to differential conversion Pin selectable input range with overrange Input ranges with 4.096 V REFBUF: ±10 V, ±5 V, ±4.096 V, ±2.5 V, and ±1.5 V Gain/attenuation options: 0.37, 0.73, 0.87, 1.38, and 2.25 Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball CSP_BGA package 2.5× footprint reduction vs. discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL error: ±3.1 ppm typical, ±6.2 ppm maximum (Gain = 0.73, gain = 0.87, gain = 1.38, gain = 2.25) SINAD: 90.4 dB typical at 20 kHz (gain = 0.73) THD: −117 dB at 1 kHz, −110 dB at 100 kHz (gain = 0.73) Gain error: ±0.005%FS typical Gain error drift: ±0.13 ppm/°C typical On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: −40°C to +85°C

8 Channel, PDM to I2S/TDM Converter Features: 8 channels of PDM audio inputs from digital microphones 16×, 32×, or 64× decimation ratio of PDM to PCM audio data 24-bit resolution to support high sound pressure level (SPL) microphones 126 dB A-weighted SNR 4 kHz to 192 kHz output sampling rate Bit clock rates of 64×, 128×, 192×, 256×, 384×, or 512× the output sampling rate Dual output PDM clocks Automatic PDM clock generation Automatic power-down when BCLK removed Selectable I2C control or hardware mode operation 1.2 mA DVDD operating current for 8 channels at 48 kHz frequency sampling rate and 1.8 V supply Slave I2S or TDM output interface Up to TDM-16 supported Configurable TDM slot routing and sizes I/O supply voltage from 1.70 V to 3.63 V DVDD supply voltage from 1.10 V to 1.98 V <5 μA typical DVDD shutdown current 16-lead, 3 mm × 3 mm, 0.50 mm pitch LFCSP Power-on reset

0.4 CMOS, Dual DPDT Switch in WLCSP/LFCSP/TSSOP Features: 1.8 V to 5.5 V operation Ultralow on resistance 0.4 Ω typical 0.6 Ω maximum at 5 V supply Excellent audio performance, ultralow distortion 0.07 Ω typical 0.14 Ω maximum RON flatness High current carrying capability 400 mA continuous 600 mA peak current at 5 V Automotive temperature range: −40°C to +125°C Rail-to-rail switching operation Typical power consumption (<0.1 μW)