Low Noise Single-Ended to Differential Converter/ADC Driver Features: Rail-to-Rail Input and Outputs Fast Settling Time: 240ns, 0.01%, 8VP-P Output Step 1.9nV/√Hz Input-Referred Op Amp Noise High Impedance Input –3dB Bandwidth: 33MHz 2.7V to 12V Supply Operation No External Gain Resistors Required 4.8mA Supply Current Low Power Shutdown Low Distortion (HD2/HD3): –102dBc/–97dBc at 100kHz, VOUTDIFF = 4VP-P Low Offset Voltage: ±400μV Max High DC Linearity: <±1LSB, 16-Bit, 8VP-P Low Input Current Noise: 1.1pA/√Hz 3mm × 3mm 8-Pin DFN and 8-Lead MSOP Packages

Precision 1.7 g, 5 g, 18 g Dual-Axis iMEMS Accelerometer Features: High performance dual-axis accelerometer on a single IC chip 5 mm × 5 mm × 2 mm LCC package 1 mg resolution at 60 Hz Low power: 700 µA at VS = 5 V (typical) High zero g bias stability High sensitivity accuracy –40°C to +125°C temperature range X and Y axes aligned to within 0.1° (typical) BW adjustment with a single capacitor Single-supply operation 3500 g shock survival RoHS-compliant Compatible with Sn/Pb- and Pb-free solder processes

Single-Supply, Multichannel, 125 kSPS, 24-Bit, Sigma-Delta ADC with 10 V Inputs Features:24-bit ADC with integrated AFEFast and flexible output rate: 2.5 SPS to 125 kSPSChannel scan data rate of 24,845 SPS per channel (40.25 s settling)85 dB common mode rejection of 50 Hz and 60 Hz at 20 SPS per channel10 V inputs, either 8 differential or 16 single-endedVIN pin absolute maximum rating 65 VAbsolute input pin voltage up to 20 VMinimum 1 M impedanceOn-chip 2.5 V reference0.12% initial accuracy at 25C, 5 ppm/C (typical) driftInternal or external clockPower suppliesAVDD = 4.5 V to 5.5 VIOVDD = 2 V to 5.5 VTotal current consumption AVDD + IOVDD (IDD) = 10.4 mATemperature range: 40C to +105C3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)SPI, QSPI, MICROWIRE, and DSP compatible

Silicon SPDT Switch, Reflective, 35 GHz to 44 GHz Features:Reflective design Low insertion loss: 1.8 dB at 44 GHz High isolation: 28 dB at 44 GHz High input linearity 0.1 dB power compression (P0.1dB): 37 dBm Third-order intercept (IP3): 52 dBm High RF power handling: 28 dBm average 36 dBm peak Single supply operation: 3.3V Internal negative voltage generator (NVG) RF settling time (0.1 dB final RF output): 45 ns 20-terminal, 3 mm × 3 mm, land grid array package Pin compatible with the ADRF5300: 24 GHz - 32 GHz

0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Features:Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.1 dB up to 18 GHz 2.9 dB up to 26 GHz 4.8 dB up to 40 GHz Attenuation accuracy with impedance match ±(0.10 + 1.0% of attenuation state) up to 18 GHz ±(0.15 + 0.8% of attenuation state) up to 26 GHz ±(0.35 + 2.5% of attenuation state) up to 40 GHz Typical step error with impedance match ±0.18 dB up to 18 GHz ±0.23 dB up to 26 GHz ±0.51 dB up to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 27 dBm IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF settling time (0.1 dB of final RF output): 250 ns 24-terminal, 4 mm × 4 mm LGA package Pin compatible with ADRF5720, low frequency cutoff version

Dual Narrow/Wideband RF Transceiver Features: 2 2 highly integrated transceiver Frequency range of 30 MHz to 6000 MHz Transmitter and receiver bandwidth from 12 kHz to 40 MHz Two fully integrated, fractional-N, RF synthesizers LVDS and CMOS synchronous serial data interface options Low power monitor and sleep modes Multichip synchronization capabilities Fast frequency hopping Dynamic profile switching for dynamic data rates and sample rates Fully programmable via a 4-wire SPI 12 mm 12 mm, 196-ball CSP_BGA

Integrated Dual RF Receiver Features: Dual receivers Maximum Receiver BW: 200 MHz Fully integrated, fractional-N, RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuneable range: 75 MHz to 6000 MHz

Integrated Dual RF Tx, Rx, and Observation Rx Features: Dual transmitters Dual receivers Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz

High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications Features: 400MHz SIMD SHARC Core, capable of 2.4 GFLOPS peak performance 2Mbits SRAM; 6 Mbits customer-definable ROM High bandwidth, 32-bit external memory interface supporting glue-less interface to SDRAM, SRAM, and FLASH Digital Audio Interface (DAI) enabling user-definable access to system peripherals including 8 serial ports (SPORTs), S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and 4 precision clock generators. Digital Peripheral Interface (DPI) enabling user-definable access to system peripherals including 2 SPI-compatible ports, 2 UARTs, 3 full-featured timers, and a two-wire interface compliant to the I2C standard. 34 zero-overhead DMA channels 16 Pulse Width Modulation (PWM) channels 208-lead LQFP-EP and 256-ball SBGA packages Commercial and industrial temperature ranges Maximum core performance is reduced for LQFP package

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications