The AD5593R has eight input/output (I/O) pins, which can beindependently configured as digital-to-analog converter (DAC)outputs, analog-to-digital converter (ADC) inputs, digital outputs,or digital inputs. When an I/O pin is configured as an analogoutput, it is driven by a 12-bit DAC. The output range of theDAC is 0 V to VREF or 0 V to 2 × VREF. When an I/O pin isconfigured as an analog input, it is connected to a 12-bit ADCvia an analog multiplexer. The input range of the ADC is 0 V toVREF or 0 V to 2 × VREF. The I/O pins can also be configured tobe general-purpose, digital input or output (GPIO) pins. Thestate of the GPIO pins can be set or read back by accessing theGPIO write data register and GPIO read configuration registers,respectively, via an I2C write or read operation.The AD5593R has an integrated 2.5 V, 20 ppm/°C reference thatis turned off by default and an integrated temperature indicatorthat gives an indication of the die temperature. The temperaturevalue is read back as part of an ADC read sequence.The AD5593R is available in 16-lead TSSOP and LFCSP, as wellas a 16-ball WLCSP, and operates over a temperature range of−40°C to +105°C.APPLICATIONS Control and monitoring General-purpose analog and digital I/O

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package. The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins. The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI. The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios

The AD7124-8 is a low power, low noise, completely integratedanalog front end for high precision measurement applications.The device contains a low noise, 24-bit Σ-Δ analog-to-digitalconverter (ADC), and can be configured to have 8 differentialinputs or 15 single-ended or pseudo differential inputs. The onchiplow gain stage ensures that signals of small amplitude canbe interfaced directly to the ADC.One of the major advantages of the AD7124-8 is that it gives theuser the flexibility to employ one of three integrated powermodes. The current consumption, range of output data rates,and rms noise can be tailored with the power mode selected.The device also offers a multitude of filter options, ensuring thatthe user has the highest degree of flexibility.The AD7124-8 can achieve simultaneous 50 Hz and 60 Hzrejection when operating at an output data rate of 25 SPS (singlecycle settling), with rejection in excess of 80 dB achieved at loweroutput data rates.The AD7124-8 establishes the highest degree of signal chainintegration. The device contains a precision, low noise, lowdrift internal band gap reference and accepts an externaldifferential reference, which can be internally buffered. Otherkey integrated features include programmable low drift excitationcurrent sources, burnout currents, and a bias voltage generator,which sets the common-mode voltage of a channel to AVDD/2.The low-side power switch enables the user to power downbridge sensors between conversions, ensuring the absoluteminimal power consumption of the system. The device alsoallows the user the option of operating with either an internalclock or an external clock.The integrated channel sequencer allows several channels to beenabled simultaneously, and the AD7124-8 sequentially convertson each enabled channel, simplifying communication with thedevice. As many as 16 channels can be enabled at any time, achannel being defined as an analog input or a diagnostic suchas a power supply check or a reference check. This uniquefeature allows diagnostics to be interleaved with conversions.The AD7124-8 also supports per channel configuration. Thedevice allows eight configurations or setups. Each configurationconsists of gain, filter type, output data rate, buffering, andreference source. The user can assign any of these setups on achannel by channel basis.The AD7124-8 also has extensive diagnostic functionalityintegrated as part of its comprehensive feature set. Thesediagnostics include a cyclic redundancy check (CRC), signalchain checks, and serial interface checks, which lead to a morerobust solution. These diagnostics reduce the need for externalcomponents to implement diagnostics, resulting in reducedboard space needs, reduced design cycle times, and cost savings.The failure modes effects and diagnostic analysis (FMEDA) of atypical application has shown a safe failure fraction (SFF) greaterthan 90% according to IEC 61508.The device operates with a single analog power supply from 2.7 Vto 3.6 V or a dual 1.8 V power supply. The digital supply has arange of 1.65 V to 3.6 V. It is specified for a temperature rangeof −40°C to +125°C. The AD7124-8 is housed in a 32-leadLFCSP package.Note that, throughout this data sheet, multifunction pins, suchas DOUT/RDY, are referred to either by the entire pin name orby a single function of the pin, for example, RDY, when onlythat function is relevant.Applications Temperature measurement Pressure measurement Industrial process control Instrumentation Smart transmitters

The AD7177-2 is a 32-bit low noise, fast settling, multiplexed,2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digitalconverter (ADC) for low bandwidth inputs. It has a maximumchannel scan rate of 10 kSPS (100 µs) for fully settled data. Theoutput data rates range from 5 SPS to 10 kSPS.The AD7177-2 integrates key analog and digital signal conditioningblocks to allow users to configure an individual setup foreach analog input channel in use. Each feature can be user selectedon a per channel basis. Integrated true rail-to-rail buffers on theanalog inputs and external reference inputs provide easy to drivehigh impedance inputs. The precision 2.5 V low drift (2 ppm/°C)band gap internal reference (with output reference buffer) addsembedded functionality to reduce external component count.The digital filter allows simultaneous 50 Hz and 60 Hz rejectionat a 27.27 SPS output data rate. The user can switch betweendifferent filter options according to the demands of eachchannel in the application. The ADC automatically switchesthrough each selected channel. Further digital processingfunctions include offset and gain calibration registers,configurable on a per channel basis.The device operates with a 5 V AVDD1 supply, or with ±2.5 VAVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies.The specified operating temperature range is −40°C to +105°C.The AD7177-2 is available in a 24-lead TSSOP package.Applications Process control: PLC/DCS modules Temperature and pressure measurement Medical and scientific multichannel instrumentation Chromatography

The AD7402 is a high performance, second-order, Σ-Δ modulator that converts an analog input signal into a high speed, single-bit data stream, with on-chip digital isolation based on Analog Devices, Inc., iCoupler® technology. The AD7402 operates from a 4.5 to 5.5 V (VDD1) power supply and accepts a differential input signal of ±250 mV (±320 mV full scale). The differential input is ideally suited to shunt voltage monitoring in high voltage applications where galvanic isolation is required.The analog input is continuously sampled by a high performance analog modulator, and converted to a ones density, digital output stream with a data rate of 10 MHz. The original information can be reconstructed with an appropriate digital filter to achieve 87 dB signal to noise ratio (SNR) at 39 kSPS. The serial input/output can use a 3 V to 5.5 V or a 3.3 V supply (VDD2).The serial interface is digitally isolated. High speed complementary metal oxide semiconductor (CMOS) technology, combined with monolithic transformer technology, means the on-chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. The AD7402 device is offered in an 8-lead wide body SOIC package and has an operating temperature range of −40°C to +105°C.Safety and regulatory approvals UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 1250 VPEAKApplications Shunt current monitoring AC motor controls Power and solar inverters Wind turbine inverters Data acquisition systems Analog-to-digital and opto-isolator replacements

Attenuators 10dB LSB 1-Bit dig atten SMT DC - 5 GHz

Flip-Flops 26GHz Fast RT T-FF w/ Reset

FAILSAFE SWITCH, SPST, 6GHZ, SOT-26;

VCO, W/HALF FREQ O/P, 7.8-8.8GHZ, QFN32;

The ADCMP606 and ADCMP607 are very fast comparatorsfabricated on XFCB2, an Analog Devices, Inc., proprietaryprocess. These comparators are exceptionally versatile and easyto use. Features include an input range from VEE ? 0.5 V toVCCI + 0.2 V, low noise, CML-compatible output drivers, andTTL-/CMOS-compatible latch inputs with adjustable hysteresisand/or shutdown inputs.The devices offer 1.25 ns propagation delay with 2.5 ps rmsrandom jitter (RJ). Overdrive and slew rate dispersion aretypically less than 50 ps.A flexible power supply scheme allows the devices to operatewith a single +2.5 V positive supply and a ?0.5 V to +2.7 Vinput signal range up to a +5.5 V positive supply with a ?0.5 Vto +5.7 V input signal range. The ADCMP607 features splitinput/output supplies with no sequencing restrictions tosupport a wide input signal range with independent outputswing control and power savings.The CML-compatible output stage is fully back-matched forsuperior performance. The comparator input stage offers robustprotection against large input overdrive, and the outputs do notphase reverse when the valid input signal range is exceeded. Onthe ADCMP607, latch and programmable hysteresis features arealso provided with a unique single-pin control option.The ADCMP606 is available in a 6-lead SC70 package and theADCMP607 is available in a 12-lead LFCSP package.Applications High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE)