4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

4T4R Direct RF Receiver and Transmitter Features: Flexible, reconfigurable radio common platform design Transmitter/receiver channel bandwidth up to 1.2 GHz (4T4R) RF DAC/RF ADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RF clock input option Versatile digital features Selectable interpolation and decimation filters Configurable DDCs and DUCs 8 fine complex DUCs (FDUC) and 4 coarse complex DUCs (CDUC) 8 fine complex DDCs (FDDC) and 4 coarse complex DDCs (CDDC) FDUCs and FDDCs are fully bypassable 2 independent 48-bit NCOs per DUC or DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Supports real or complex digital data (8-, 12-, or 16-bit) Auxiliary features ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins support toggling between modes TDD power savings option and sharing ADCs SERDES JESD204B or JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver (JRx) Supports Subclass 1 Supports multidevice synchronization 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

FAILSAFE SWITCH, SPST, 6GHZ, SOT-26;

FAILSAFE SWITCH, SPST, 6GHZ, SOT-26;

VCO, W/HALF FREQ O/P, 7.8-8.8GHZ, QFN32;

EVALUATION KIT, DATA ACQUISITION;

RF Mixer DBL-BAL mix SMT 9 - 15 GHz

The AD532 is the first pretrimmed single chip monolithic multiplier/divider. It guarantees a maximum multiplying error of ±1.0% and a ±10 V output voltage without the need for any external trimming resistors or output op amp. Because the AD532 is internally trimmed, its simplicity of use provides design engineers with an attractive alternative to modular multipliers, and its monolithic construction provides significant advantages in size, reliability and economy. Further, the AD532 can be used as a direct replacement for other IC multipliers that require external trim networks (such as the AD530).APPLICATIONS Multiplication, division, squaring, square rooting Algebraic computation Power measurements Instrumentation applications Available in chip form

The AD5330 / AD5331 / AD5340 / AD5341 are single 8-/10-/12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 μA at 3 V and feature a power-down mode that further reduces the current to 80 nA. The devices incorporate an on-chip output buffer that can drive the output to both supply rails, but the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input.The AD5330 / AD5331 / AD5340 / AD5341 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR. The GAIN pin allows the output range to be set at 0 V to VREF or 0 V to 2 × VREF.Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.An asynchronous CLR input is also provided, which resets the contents of the input register and the DAC register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.The AD5330 / AD5331 / AD5340 / AD5341 are available in thin shrink small outline packages (TSSOP).APPLICATIONS Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators Industrial process control

The AD534 is a monolithic laser trimmed four-quadrant multiplier divider having accuracy specifications previously found only in expensive hybrid or modular products. A maximum multiplication error of ±0.25% is guaranteed for the AD534L without any external trimming. Excellent supply rejection, low temperature coefficients and long-term stability of the on-chip thin film resistors and buried Zener reference preserve accuracy even under adverse conditions of use. It is the first multiplier to offer fully differential, high impedance operation on all inputs, including the Z input, a feature that greatly increases its flexibility and ease of use. The scale factor is pretrimmed to the standard value of 10.00 V; by means of an external resistor, this can be reduced to values as low as 3 V.The wide spectrum of applications and the availability of several grades commend this multiplier as the first choice for all new designs. The AD534J (±1% maximum error), AD534K (±0.5% maximum), and AD534L (±0.25% maximum) are specified for operation over the 0°C to +70°C temperature range. The AD534S (±1% maximum) and AD534T (±0.5% maximum) are specified over the extended temperature range, −55°C to +125°C. All grades are available in hermetically sealed TO-100 metal cans and SBDIP packages. AD534K, AD534S, and AD534T chips are also available.APPLICATIONSHigh quality analog signal processingDifferential ratio and percentage computationsAlgebraic and trigonometric function synthesisWideband, high crest rms-to-dc conversionAccurate voltage controlled oscillators and filtersAvailable in chip form