The HMC463 is a GaAs MMIC PHEMT Low Noise AGC Distributed Amplifier die which operates between 2 and 20 GHz. The amplifier provides 14 dB of gain, 2.5 dB noise figure and 19 dBm of output power at 1 dB gain compression while requiring only 60 mA from a +5V supply. An optional gate bias (Vgg2) is provided to allow Adjustable Gain Control (AGC) of 10 dB typical. Gain flatness is excellent at ±0.15 dB from 6 - 18 GHz making the HMC463 ideal for EW, ECM and RADAR applications. The HMC463 amplifiercan easily be integrated into Multi-Chip-Modules (MCMs) due to its small size. All data is with the chip in a 50 Ohm test fixture connected via 0.025mm (1 mil) diameter wire bonds of minimal length 0.31mm (12 mils).Applications Telecom Infrastructure  Microwave Radio & VSAT  Military & Space  Test Instrumentation  Fiber Optics

The HMC463LP5(E) is a GaAs MMIC pHEMT Low Noise AGC Distributed Amplifier packaged in a leadless 5x5 mm surface mount package which operates between 2 and 20 GHz. The amplifier provides 13 dB of gain, 2.8 dB noise figure and 18 dBm of output power at 1 dB gain compression while requiring only 60mA from a +5V supply. An optional gate bias (Vgg2) is provided to allow Adjustable Gain Control (AGC) of 8 dB typical. Gain flatness is excellent at 0.5 dB from 6 - 18 GHz making the HMC463LP5(E) ideal for EW, ECM RADAR and test equipment applications. The HMC463LP5(E) LNA I/Os are internally matched to 50 Ohms and are internally DC blocked.Applications Telecom Infrastructure  Microwave Radio & VSAT  Military EW, ECM & C³I  Test Instrumentation  Fiber Optics

The HMC478 devices are SiGe, heterojunction bipolar transistor (HBT), gain block MMIC, SMT amplifiers covering dc to 4 GHz. These amplifiers can be used as cascadable 50 Ω RF/IF gain stages as well as LO or PA drivers with up to 17 dBm or 20 dBm output power. These amplifiers offer 22 dB or 23 dB of gain with 31 dBm, 32 dBm, or 33 dBm output IP3 at 850 MHz, while requiring only 62 mA from a single positive supply. The Darlington feedback topology results in reduced sensitivity to normal process variations and excellent gain stability over temperature while requiring a minimal number of external bias components.Applications Cellular/PCS/3G/4G Fixed wireless and WLAN CATV, cable modem, and direct broadcast satellite (DBS) Microwave radio and test equipment 

The HMC659LC5 is a GaAs MMIC PHEMT Distributed Power Amplifier which is housed in a leadless 5x5 mm RoHS compliant ceramic SMT package operating between DC and 15 GHz. The amplifier provides 19 dB of gain, +35 dBm output IP3 and +27.5 dBm of output power at 1 dB gain compression, while requiring 300mA from a +8V supply.Gain flatness is excellent at ±0.7 dB from DC - 15 GHz making the HMC659LC5 ideal for EW, ECM, Radar and test equipment applications. The HMC659LC5 amplifier I/Os are internally matched to 50 ohms with no external components. The HMC659LC5 is compatible with high volume surface mount manufacturing techniques.Applications Telecom Infrastructure Microwave Radio & VSAT Military & Space Test Instrumentation Fiber Optics

The HMC764LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) with an Integrated Voltage Controlled Oscillator (VCO). The input reference frequency range is 100 kHz to 220 MHz while the advanced delta-sigma modulator design in the fractional PLL allows both ultra-fine step sizes and very low spurious products. The highly integrated structure provides excellent phase noise performance over temperature, shock and process. The HMC764LP6CE is packaged in a leadless QFN 6 x 6 mm surface mount package. The output power is 15 dBm typical, making the HMC764LP6CE ideal for driving the LO port of many of Hittite’s Hi Linearity and I/Q mixer products.For theory of operation and register map refer to the 'PLLs w/ Integrated VCO - Microwave VCOs' Operating Guide.Applications VSAT Radio Point-to-Point / Multi-Point Radio Test Equipment & Industrial Control Military End-Use Phased Array Applications

The HMC769LP6CE is a fully functioned Fractional-N Phase-Locked-Loop (PLL) Frequency Synthesizer with an integrated Voltage Controlled Oscillator (VCO). The input reference frequency range is DC to 350 MHz while the advanced delta-sigma modulator design in the fractional synthesizer allows both ultra-fine step sizes and very low spurious products. The highly integrated structure provides excellent phase noise performance over temperature, shock and process. In addition, the HMC769LP6CE offers frequency sweep and modulation features, external triggering, double-buffering, exact frequency control, phase modulation and more. The HMC769LP6CE is packaged in a leadless QFN 6 x 6 mm surface mount package.For theory of operation and register map refer to the 'PLLs w/ Integrated VCO - Microwave VCOs' Operating Guide.Applications VSAT Radio Microwave Point-To-Point Radios Test Equipment & Industrial Control Military End-Use Phased Array Applications FMCW Radar Systems

The HMC851LC3C is a XOR/XNOR gate function designed to support data transmission rates of up to 28 Gbps, and clock frequencies as high as 28 GHz. The HMC851LC3C also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.All input signals to the HMC851LC3C are terminated with 50 Ohms to ground on-chip, and may be either AC or DC coupled. The differential outputs of the HMC851LC3C may be either AC or DC coupled. Outputs can be connected directly to a 50 Ohm to ground terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ohms to a nonground DC voltage. The HMC851LC3C operates from a single -3.3V DC supply, and is available in a ceramic RoHS compliant 3x3 mm SMT package.APPLICATIONS RF ATE Applications Broadband Test & Measurement Serial Data Transmission up to 28 Gbps

HMC983LP5E is a fractional frequency divider targeted for fractional-N frequency synthesis, and stand-alone low noise frequency divider applications that require exceptional spurious performance.Although the HMC983LP5E can work with any VCO and/or compatible Phase Detector, best performance and features will be achieved when paired with the companion part, the HMC984LP4E.Fabricated in SiGe BiCMOS process, the HMC983LP5E features a 48-bit Delta Sigma Fractional Modulator (DSM) with programmable phase accumulator size, enabling precise control of frequency step size and resolution. Integrated DSM can generate frequencies with nearly 0 Hz frequency error. The DSM also includes a built-in programmable frequency sweep capability, with various automatic and user defined sweep modes and triggering options, including hardware trigger pin, or SPI trigger with optional delayed trigger.HMC983LP5E is a versatile part capable of various configurations. It has 5 general purpose I/Os (GPIOs). DSM outputs are made available from the GPIO port, enabling the HMC983LP5E to import and/or export DSM sequences for various configuration options.HMC983LP5E divider outputs are differential, open collector with programmable current to accommodate different off-chip loads.Applications Test Equipment Portable Instruments High Performance Fractional-N Frequency Synthesizers with Ultra Low Spurious Stand-Alone Divider and/or Delta-Sigma Modulator

The HMC992LP5E is an IF analog controlled variable gain amplifier composed of two identical voltage variable attenuators in combination with an InGaP HBT gain block MMIC amplifier which operates from 0.1 to 0.8 GHz, and can be controlled to provide anywhere from -10 dB attenuation, to 40 dB of gain. The HMC992LP5E delivers noise figure of 6 dB in its maximum gain state, with output IP3 of up to +40 dBm. The HMC992LP5E is housed in a RoHS compliant 5x5 mm QFN leadless package, and requires no external matching components.Applications Cellular/3G Infrastructure WiBro / WiMAX / 4G Microwave Radio & VSAT Test Equipment and Sensors IF & RF Applications

The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver.The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output.The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition.The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807.The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance.The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater.Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency.The AD807 consumes 140 mW and operates from a single power supply at either +5 V or –5.2 V.