8-Channel PMBus Power System Manager Featuring Accurate Output Voltage Measurement Features: Sequence, Trim, Margin and Supervise Eight Power Supplies Manage Faults, Monitor Telemetry and Create Fault Logs PMBus™ Compliant Command Set Supported by LTpowerPlay® GUI Margin or Trim Supplies to Within 0.25% of Target Fast OV/UV Supervisors Per Channel Coordinate Sequencing and Fault Management Across Multiple LTC PSM Devices Automatic Fault Logging to Internal EEPROM Operate Autonomously without Additional Software Internal Temperature and Input Voltage Supervisors Accurate Monitoring of Eight Output Voltages, Input Voltage and Internal Die Temperature I2C/SMBus Serial Interface Can Be Powered from 3.3V, or 4.5V to 15V Programmable Watchdog Timer 100% Pin-Compatible Upgrade to the LTC2978/LTC2978A Available in 64-Pin 9mm × 9mm QFN PackageAEC-Q100 Qualified for Automotive Applications

35V/3.2A Multi-Cell Lithium-Ion Step-Down Battery Charger with PowerPath and I2C Telemetry Features: Li-Ion/Polymer Battery Charger with Termination Wide Charging Input Voltage Range: 4.5V to 35V High Efficiency Synchronous Operation 16-Bit Digital Telemetry System Monitors VBAT, IBAT, RBAT, TBAT, TDIE, VIN, IIN, VOUT Charges 1-8 Lithium-Ion/Polymer Cells Input Undervoltage Charge Current Limit Loop Input MPPT for Solar Panel Inputs Input Current Limit Prioritizes System Load Output Low Loss PowerPath™ Instant-On Operation with Discharged or Missing Battery JEITA Temperature Controlled Charging Pin Compatible with LiFePO4 and SLA Versions

Low Input Bias Current, Wide BW JFET Precision Dual Op Amp Features: Low Noise 6 nV/√Hz Low Offset Voltage: 100 µV Max Low Input Bias Current 10 pA Max Fast Settling: 600 ns to 0.01% Low Distortion Unity Gain Stable No Phase Reversal Dual-Supply Operation: ±5 V to ±13 V

10 MHz, G = 1, 10, 100, 1000 iCMOS Programmable Gain Instrumentation Amplifier Features: Small package: 10-lead MSOP Programmable gains: 1, 10, 100, 1000 Digital or pin-programmable gain setting Wide supply: ±5 V to ±15 V Excellent dc performance High CMRR: 100 dB (minimum), G = 100 Low gain drift: 10 ppm/°C (maximum) Low offset drift: 1.2 µV/°C (maximum), G = 1000 See data sheet for additional features

2.5A Supercapacitor Backup Power Manager Features: 2.5A Step-Down Supercapacitor Charger and 2.5A Step-Up Backup Supply 6.5A Switches for 2.5A Backup from One Supercapacitor or Two in Series Input Current Limit Prioritizes Load over Charge Current Input Disconnect Switch Isolates Input During Backup Automatic Seamless Switch-Over to Backup Mode Internal Supercapacitor Balancer (No External Resistors) Programmable Charge Current and Charge Voltage Input Power Fail Indicator System Power Good Indicator Optional OVP Circuitry Protects Device to >60V Constant Frequency Operation Thermally Enhanced 24-Lead 4mm × 5mm QFN Package

25A, Dual PolyPhase Regulator with Digital Power System Management Features: PMBus/I2C Compliant Serial Interface Telemetry Read-Back Includes VIN, IIN, VOUT, IOUT, Temperature and Faults Programmable Voltage, Current Limit, Digital Soft-Start/Stop, Sequencing, Margining, OV/UV/OC Sub-Milliohm DCR Current Sensing Digitally Adjustable Loop Compensation Parameters 0.5% Output Voltage Accuracy Over Temperature Integrated Input Current Sense Amplifier Internal EEPROM with ECC and Fault Logging Integrated N-Channel MOSFET Gate Drivers

3GHz to 20GHz Microwave Mixer with Wideband DC to 6GHz IF Features:Integrated LO Buffer: 0dBm LO Drive50 Wideband Matched RF and LO PortsWide IF Bandwidth: DC to 6GHzUpconversion or DownconversionHigh IIP3:+22.5dBm at 10GHz+18.3dBm at 17GHz+14.6dBm Input P1dB at 10GHz8dB Conversion Loss at 10GHz3.3V/132mA SupplyFast Turn ON/OFF for TDD Operation3mm × 2mm, 12-Lead QFN Package

Digitally Programmable Sensor Signal Amplifier with EMI Filters Features: EMI filters at input pins Specified from −40°C to +140°C Low offset voltage: 10 μV maximum Low input offset voltage drift: 65 nV/°C maximum High CMRR: 94 dB minimum Digitally programmable gain and output offset voltage Programmable output clamp voltage Open and short wire fault detection Low-pass filtering Single-wire serial interface Stable with any capacitive load SOIC_N and LFCSP_VQ packages 4.5 V to 5.5 V operation

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity

4T2R Direct RF Transmitter and Observation Receiver Features: Flexible reconfigurable radio common platform design Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R) RFDAC/RFADC RF frequency range up to 7.5 GHz On-chip PLL with multichip synchronization External RFCLK input option Versatile digital features Configurable digital up/down conversion (DDC and DUC) 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs, 2 independent 48-bit NCO per DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Programmable delay and gain per transmit data path Coarse DDC delay adjust for DPD observation path Auxiliary features Power amplifier downstream protection circuitry On-chip temperature monitoring unit Programmable GPIO pins supporting different user configurations ADC clock driver with selectable divide ratios TDD power savings option and sharing ADCs SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes per each DAC and ADC JESD204B compatible with maximum 15.5 Gbps lane rate JESD204C compatible with maximum 24.75 Gbps lane rate Supports real or complex digital data (8-bit, 12-bit, 16-bit, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch