Demonstration circuit 3033A is a triple output synchronous step-up/dual step-down supply featuring the LTC7817. The demonstration circuit is designed for two buck outputs 5V/10A, 3.3V/10A supplied by a boosted 10V output. Benefiting from this feature, the buck outputs are able to maintain regulation over a wide input voltage range of 4.5V to 36V which is suitable for automotive or other battery fed applications. Also, the demonstration circuit uses a drop-in layout whereas the main buck circuit components fit in an area of ¾-inch by 1½-inch, while the main boost circuit area is ¾-inch by 1¾-inch. The package style for the LTC7817 is a 38-pin exposed pad QFN. The main features of the board include rail tracking (buck channels only), an internal 5V linear regulator for bias, separated RUN pins for each output, a PGOOD signal (CH1 only), and a mode selector that allow the converter to run in forced continuous mode (FCM), pulse-skipping (PSM) or Burst Mode® operation (BURST). Synchronization to an external clock is also possible. The LTC7817 data sheet gives a complete description of these parts, operation and application information. The data sheet must be read in conjunction with this quick start guide for demo circuit 3033A.

The LTC4126-ADJ is a low-power wireless single-cell Li-Ion battery charger with an integrated step-down DC/DC regulator. The step-down regulator is a low-noise multimode charge pump which is powered from the battery and provides a regulated 1.2V at the output. The switching frequency is set to either 50kHz or 75kHz depending on the mode to keep any switching noise out of the audible range.The constant-current constant-voltage Li-Ion battery charger has automatic recharge, automatic termination by safety timer, and battery temperature monitoring via an NTC pin. Charge current is programmable from 1mA to 50mA via an external resistor. Undervoltage protection disconnects the battery from all loads when the battery voltage is below 3.0V.The small package and minimal external component count make the LTC4126-ADJ and its variants suitable for hearing aid applications and other low power portable devices. See the chart in the data sheet.APPLICATIONSHearing AidsLow Power Li-Ion Powered DevicesWireless HeadsetsIoT Wearables

Demonstration circuit DC3082A-C features the LTM4681: the wide input and output voltage range, high efficiency and power density, high current PolyPhase® single output DC/DC step-down μModule® regulator with digital power system management. DC3082A-C is configured as 16-phase single output using 4× LTM4681. The factory default input voltage is 12V typical, output voltage is 1V at 480A typical or 500A peak with recommended 400LFM forced airflow. The demo board output voltages can be adjusted from 0.6V to 1V. Programming the output voltages to any value that is greater than 1V, requires derating output current based on thermal derating curves provided in the data sheet of the LTM4681. Heat sink or other appropriate electronic cooling systems can also be used in conjunction with forced airflow to further optimize the output power when the output is on and loaded with maximum output current. The factory default switching frequency is preset at 350kHz typical. DC3082A-C comes with PMBus interface and digital power system management functions. An onboard 12-pin connector is available for users to connect the dongle DC1613A to the demo board, provides an easy way to communicate and program the part using LTpowerPlay® software development tool. LTpowerPlay software and I2C/PMBus/SMBus dongle DC1613A allows users to monitor real time telemetry of input and output voltages, input and output current, switching frequency, internal IC die temperatures, power stage component temperatures and fault logs. Programmable parameters include device address, output voltages, control loop compensation, switching frequency, phase interleaving, DCM or CCM mode of operation, digital soft-start, sequencing and time based shutdown, fault responses to input and output overvoltage, output overcurrent, IC die and power component overtemperature. The LTM4681 is available in a thermally enhanced, low profile 330-Lead (15mm × 22mm × 8.17mm) BGA package. It is recommended to read the data sheet and the demo manual of LTM4681 prior to use or making any hardware changes to DC3082A-C. LTpowerPlay software can be downloaded here. USB to PMBus Controller Dongle DC1613A for use with LTpowerPlay is available here.

The LTC3307A is a very small, high efficiency, low noise, monolithic synchronous 3A step-down DC/DC converter operating from a 2.25V to 5.5V input supply. Using constant frequency, peak current mode control at switching frequencies 1MHz to 3MHz and minimum on-time as low as 22ns, this regulator achieves fast transient response with small external components. Silent Switcher architecture minimizes EMI emissions.The LTC3307A operates in forced continuous or pulse skip mode for low noise, or low-ripple Burst Mode operation for high efficiency at light loads, ideal for battery-powered systems. The IC regulates output voltages as low as 500mV. Other features include output overvoltage protection, short-circuit protection, thermal shutdown, clock synchronization, and up to 100% duty cycle operation for low dropout. The device is available in a low profile 12-lead 2mm ? 2mm ? 0.74mm LQFN package with exposed pad for low thermal resistance.APPLICATIONS Optical Networking, Servers, Telecom Automotive, Industrial, Communications Distributed DC Power Systems (POL) FPGA, ASIC, ?P Core Supplies Battery Operated Systems

The LTC1923 is a pulse width modulator intended for thermoelectric cooler (TEC) or heater applications requiring either unidirectional or bidirectional drive circuits. All of the necessary control circuitry and two sets of complementary output drivers are integrated into the LTC1923 to drive a full bridge, providing an efficient means of bidirectional current flow to the TEC. An accurate temperature control loop to stabilize the temperature of a laser diode system is easily achieved with the addition of just a few external components. Typical temperature setpoint accuracy of 0.1?C is achievable with the LTC1923. Adding an instrumentation amplifier front end allows setpoint stability of 0.01?C.The part features independent adjustable heating and cooling pulse-by-pulse current limit, current soft-start for controlled start-up, output slew rate control to reduce system noise, differential current sense and voltage amplifiers and a host of auxiliary circuits to protect the laser and provide redundant system monitoring.Applications Laser-Based Fiber Optic Links Medical Instruments CPU Temperature Regulators

The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus.The AD9648 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (?40?C to +85?C). Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDARProduct Highlights The AD9648 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families. The patented sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments. The AD9648 is packaged in a 64-lead RoHS compliant LFCSP that is pin compatible with the AD9650/AD9269/AD9268 16-bit ADC?s, the AD9258 14-bit ADC, the AD9628/AD9231 12-bit ADC?s, and the AD9608/AD9204 10-bit ADC?s, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.Applications Communications Diversity multi-band, multi-mode digital receivers 3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Radar Digital oscilloscopes High speed data acquisition systems DOCSIS CMTS upstream receive paths HFC digital reverse path receivers

The AD9714/AD9715/AD9716/AD9717 are pin-compatible, dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC? converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9714/AD9715/AD9716/AD9717 make them well-suited for portable and low power applications.PRODUCT HIGHLIGHTS Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 35 mW at 125 MSPS with a 1.8 V supply. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows easy interfacing to other components that accept common- mode levels greater than 0 V.?APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9789 is a flexible QAM encoder/interpolator/upconverter combined with a high performance, 2400 MSPS, 14-bit RF digital-to-analog converter (DAC). The flexible digital interface can accept up to four channels of complex data. The QAM encoder supports constellation sizes of 16, 32, 64, 128, and 256 with SRRC filter coefficients for all standards.The on-chip rate converter supports a wide range of baud rates with a fixed DAC clock. The digital upconverter can place the channels from 0 to 0.5 ? fDAC. This permits four contiguous channels to be synthesized and placed anywhere from dc to fDAC.The AD9789 includes a serial peripheral interface (SPI) for device configuration and status register readback. The flexible digital interface can be configured for data bus widths of 4, 8, 16, and 32 bits. It can accept real or complex data.The AD9789 operates from 1.5 V, 1.8 V, and 3.3 V supplies for a total power consumption of 1.6 W. It is supplied in a 164-ball chip scale package ball grid array for lower thermal impedance and reduced package parasitics. No special power sequencing is required. The clock receiver powers up muted to prevent start-up noise.Product Highlights Highly integrated and configurable QAM mappers, interpolators, and upconverters for direct synthesis of one to four DOCSIS- or DVB-C-compatible channels in a block. Low noise and intermodulation distortion (IMD) performance enable high quality synthesis of signals up to 1 GHz. Flexible data interface supports LVDS for improved SFDR or CMOS input data for less demanding applications. Interface is configurable from 4-bit nibbles to 32-bit words and can run at up to 150 MHz CMOS or 150 MHz LVDS double data rate (DDR). Manufactured on a CMOS process, the AD9789 uses a proprietary switching technique that enhances dynamic performance.Applications Broadband communications systems CMTS/DVB Cellular infrastructure Point-to-point wireless