Precision Micropower RMS-to-DC Converter Features: Simple to Use, Requires One Capacitor True RMS DC Conversion Using Σ Technology High Accuracy: 0.1% Gain Accuracy from 50Hz to 1kHz 0.25% Total Error from 50Hz to 1kHz High Linearity: 0.02% Linearity Allows Simple System Calibration Low Supply Current: 155μA Typ, 170μA Max Ultralow Shutdown Current: 0.1μA Constant Bandwidth: Independent of Input Voltage 800kHz –3dB, 6kHz ±1% Flexible Supplies: 2.7V to 5.5V Single Supply Up to ±5.5V Dual Supply Flexible Inputs: Differential or Single-Ended Rail-to-Rail Common Mode Voltage Range Up to 1VPEAK Differential Voltage Flexible Output: Rail-to-Rail Output Separate Output Reference Pin Allows Level Shifting Wide Temperature Range: –55°C to 125°C Small Size: Space Saving 8-Pin MSOP Package

1kHz-3GHz High Signal Level Active Mixer Features: Broadband RF, LO and IF Operation High Input IP3: >20dBm from 30MHz to 900MHz +17dBm at 1900MHz Typical Conversion Gain: 1dB SSB Noise Figure: 11dB at 900MHz 14dB at 1900MHz Integrated LO Buffer: Insensitive to LO Drive Level Single-Ended or Differential LO Drive High LO-RF Isolation Enable Function 4.5V to 5.25V Supply Voltage Range 4mm x 4mm QFN Package

Dual Smart Battery System Manager Features: SMBus Charger/Selector for Two Smart Batteries* Voltage and Current Accuracy within 0.2% of Value Reported by Battery Simplifies Construction of “Smart Battery System Manager” Includes All SMBus Charger V1.1 Safety Features Supports Autonomous Operation without a Host Allows Both Batteries to Discharge Simultaneously into Single Load with Low Loss (Ideal Diode) SMBus Switching for Dual Batteries with Alarm Monitoring for Charging Battery at All Times Pin Programmable Limits for Maximum Charge Current and Voltage Improve Safety Fast Autonomous Power Path™ Switching (<10µs) Low Loss Simultaneous Charging of Two Batteries >95% Efficient Synchronous Buck Charger AC Adapter Current Limiting* Maximizes Charge Rate SMBus Accelerator Improves SMBus Timing** Available in 48-Lead TSSOP Package

40MHz to 900MHz Quadrature Demodulator Features: RF Input Frequency Range: 40MHz to 900MHz High IIP3: 21dBm at 800MHz High IIP2: 58dBm at 800MHz I/Q Gain Mismatch: 0.3dB Max I/Q Phase Mismatch: 0.7° Noise Figure: 12.4dB at 800MHz Conversion Gain: 3.3dB at 800MHz Baseband Bandwidth: 130MHz Single Ended, 50 Matched 2XLO Input Shutdown Mode 16-Lead QFN (4mm × 4mm) Package with Exposed Pad

IC Multidisplay LED Controller Features: Step-Up/Direct-Connect Fractional Charge Pump Provides Up to 92% Efficiency Up to 400mA Continuous Output Current Independent Current and Dimming Control for 1-6 LED MAIN, 1-4 LED SUB and RGB LED Displays LED Currents Programmable Using 2-Wire I2C™ Serial Interface 1% LED Current Matching Low Noise Constant Frequency Operation* Minimal Component Count Automatic Soft-Start Limits Inrush Current 16 Exponentially Spaced Dimming States Provides 128:1 Brightness Range for MAIN and SUB Displays Up to 4096 Color Combinations for RGB Display Low Operating Current: IVIN = 180µA Tiny, Low Profile 24-Lead (4mm × 4mm × 0.75mm) QFN Package

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs  Support for lane rates up to 16 Gbps per lane  1.65 W total power per channel at 3 GSPS (default settings)  Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO  4 cascaded half-band filters  Phase coherent NCO switching Up to 4 channels available  Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity