Integrated Dual RF Receiver Features: Dual receivers Maximum Receiver BW: 200 MHz Fully integrated, fractional-N, RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuneable range: 75 MHz to 6000 MHz

RF MIXER, 2 CHANNEL, 26.5GHZ, LCC-EP-24;

DIGITAL ISOLATOR 35NS SSOP-20; No. of Channels:2 Channel; Propagation Delay:35ns; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; Interface Case Style:SSOP; No. of Pins:20Pins; Operating Temperature Min:-40°C; Operating Temperature Max:105°C; Packaging:Each; Product Range:ADUM5211 Series; Automotive Qualification Standard:-; MSL:MSL 1 - Unlimited; SVHC:No SVHC (20-Jun-2016); No. of Channels:2Channels

The AD8307 is the first logarithmic amplifier made available in an 8-lead SOIC_N package. It is a complete 500 MHz monolithic demodulating logarithmic amplifier based on the progressive compression (successive detection) technique, providing a dynamic range of 92 dB to ±3 dB law conformance and 88 dB to a tight ±1 dB error bound at all frequencies up to 100 MHz. The AD8307 is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 7.5 mA is needed. A fast acting CMOS-compatible control pin can disable the AD8307 to a standby current of 150 μA.The AD8307 operates over the industrial temperature range of −40°C to +85°C and is available in an 8-lead SOIC package and an 8-lead PDIP.Applications Conversion of signal level to decibel form  Transmitter antenna power measurement  Receiver signal strength indication (RSSI)  Low cost radar and sonar signal processing  Network and spectrum analyzers (to 120 dB)  Signal level determination down to 20 Hz  True decibel ac mode for multimeters

400 MSPS 10-Bit DAC 1.8 V CMOS Direct Digital Synthesizer Features: 400 MSPS internal clock speed Integrated 10-bit DAC 32-bit tuning word Phase noise ≤ –120 dBc/Hz at 1 kHz offset (DAC output) Excellent dynamic performance >75 dB SFDR at 160 MHz (±100 kHz offset) AOUT Serial input/output (I/O) control 1.8 V power supply Software and hardware controlled power-down 48-lead TQFP/EP package PLL REFCLK multiplier (4× to 20×) Internal oscillator; can be driven by a single crystal Phase modulation capability Multichip synchronization

Stereo PDM to I2S/TDM Converter Features: 2 channels of PDM audio inputs from digital microphones 64× decimation ratio of PDM to PCM audio data 24-bit resolution to support high sound pressure level (SPL) microphones 126 dB A-weighted SNR 4 kHz to 96 kHz output sampling rate Bit clock rates of 64×, 128×, 192×, 256×, 384×, or 512× the output sampling rate Automatic PDM clock generation Automatic power-down when BCLK is removed 0.36 mA DVDD operating current at 48 kHz sampling rate and 1.8 V supply Slave I2S or TDM output interface Up to TDM-16 supported Configurable TDM slots I/O supply voltage from 1.70 V to 3.63 V DVDD core supply voltage from 1.10 V to 1.98 V 4 μA typical DVDD shutdown current 9-ball, 1.26 mm × 1.26 mm, 0.4 mm pitch WLCSP Power-on reset

High Performance Polyphase Energy Measurement IC Features: 7 high performance analog-to-digital converters (ADCs) 101 dB signal-to-noise ratio (SNR) 10,000:1 dynamic range Wide input range: ±1 V, 0.707 V rms full scale Differential inputs ±25 ppm/°C maximum channel temperature drift (including ADC, internal VREF, and PGA drift) enabling Class 0.2 meters with standard external components Power quality measurements Line frequency: 1 measurement per phase Zero crossing detection, zero-crossing timeout Phase angle measurements Supports current transformers (CTs) and Rogowski coil (di/dt) sensors Multiple range phase/gain compensation for CTs Digital integrator for Rogowski coils Flexible waveform buffer Able to resample waveform to ensure 64 points per line cycle for ease of external harmonic analysis Events can trigger waveform storage Simplifies data collection for IEC 61000-4-7 harmonic analysis Advanced metrology feature set Total active power, volt-amperes reactive (VAR), volt-amperes (VA), watthour, VAR-hour, and VA-hour Fundamental VAR and VAR-hour Current and voltage rms per phase (xIRMS, xVRMS) Supports active energy standards: IEC 62053-21, IEC 62053-22; EN50470-3; OIML R46, ANSI C12.20 Supports reactive energy standards: IEC 62053-23, IEC 62053-4 High speed communication port 10 MHz serial peripheral interface (SPI)

ISOLATORS ROHS COMPLIANT: YES

The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI™) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP).ANALOG INTERFACEThe AD9880 is a complete 8-bit 150 MSPS monolithic analog interface optimized for capturing Component Video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports all HDTV formats (up to 1080p) and FPD resolutions up to SXGA (1280 × 1024 at 75 Hz).The analog interface includes a 150 MHz triple ADC with internal 1.25V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8V and 3.3V power supply, analog input, and Hsync. Three-state CMOS outputs may be powered from 1.8V to 3.3V. The AD9880’s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 150 MHz. PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The AD9880 also offers full sync processing for composite sync and Sync-on-Green (SOG) applications.DIGITAL INTERFACEThe AD9880 contains a HDMI v1.1 compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 × 1024 at 75 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9880 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.1 protocol.Fabricated in an advanced CMOS process, the AD9880 is provided in a space-saving 100-lead LQFP surface-mount Pb-free plastic package and is specified over the 0 ºC to 70 ºC temperature range.APPLICATIONS Advanced TV HDTV Projectors LCD Monitor

The AD8400 / AD8402 / AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kOhm, 10 kOhm, 50 kOhm or 100 kOhm has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-before-make operation.Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic.APPLICATIONS Mechanical potentiometer replacement Programmable filters, delays, time constants Volume control, panning Line impedance matching Power supply adjustment