Multiple Range, 12-Bit, Unipolar, Voltage Output DACs Features: 8 software-programmable output ranges: 0 V to +5 V, 0 V to +10 V, 0 V to +16 V, 0 V to +20 V, ±3 V, ±5 V, ±10 V, −2.5 V to +7.5 V; 5% overrange Total unadjusted error (TUE): 0.1% FSR maximum 16-bit resolution: ±2 LSB maximum INL Guaranteed monotonicity: ±1 LSB maximum Single channel, 12-bit DACs Settling time: 7.5 μs typical Integrated reference buffers Low noise: 35 nV/√Hz Low glitch: 1 nV-sec 1.8 V logic compatibility Asynchronous updating via LDAC Asynchronous RESET to zero scale/midscale DSP/microcontroller-compatible serial interface Robust 4 kV HBM ESD rating Available in 16-lead TSSOP and 16-lead LFCSP Operating temperature range: −40°C to +125°C

Single-Channel, 16-Bit Current and Voltage Output DAC with Dynamic Power Control and HART Connectivity Features: 16-bit resolution and monotonicity DPC for thermal management Current/voltage output available on a single terminal Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA, 0 mA to 24 mA, ±20 mA, ±24 mA, −1 mA to +22 mA Voltage output ranges (with 20% overrange): 0 V to 5 V, 0 V to 10 V, ±5 V, and ±10 V User-programmable offset and gain Advanced on-chip diagnostics, including a 12-bit ADC On-chip reference Robust architecture, including output fault protection EMC test standards: IEC 61000-4-6 conducted immunity (10 V, Class A) IEC 61000-4-3 radiated immunity (20 V/m, Class A) IEC 61000-4-2 ESD (±6 kV contact, Class B) IEC 61000-4-4 electrical fast transient (EFT) (±4 kV, Class B) IEC 61000-4-5 surge (±4 kV, Class B) 32-lead, 5 mm × 5 mm LFCSP −40°C to +115°C temperature range

16-Channel, 16-Bit Voltage Output denseDAC Features: Download AD5766-KGD Data Sheet. Available as Known Good Die and fully guaranteed to data sheet specifications. Complete 16-channel, 16-bit DACs 8 software-programmable output ranges: −20 V to 0 V, −16 V to 0 V, −10 V to 0 V, −10 V to +6 V, −12 V to +14 V, −16 V to +10 V, ±5 V and ±10 V Integrated DAC output buffers with ±20 mA output current capability 4 mm × 4 mm WLCSP package and 40-lead LFCSP package Integrated reference buffers 2 dither signal input pins Channel monitoring multiplexer 1.8 V logic compatibility Temperature range: −40°C to +105°C

High Precision, Impedance & Electrochemical Front End Features: Analog input 16-bit ADC with both 800 kSPS and 1.6 MSPS options Voltage, current, and impedance measurement capability Internal and external current and voltage channels Ultralow leakage switch matrix and input mux Input buffers and programmable gain amplifier Voltage DACs Dual output voltage DAC with an output range of 0.2 V to 2.4 V 12-bit VBIAS0 output to bias potentiostat 6-bit VZERO0 output to bias TIA Ultra low power: 1 µA 1 high speed, 12-bit DAC Output range to sensor: ±607 mV Programmable gain amplifier on output with gain settings of 2 and 0.05 Amplifiers, accelerators, and references 1 low power, low noise potentiostat amplifier suitable for potentiostat bias in electrochemical sensing 1 low noise, low power TIA, suitable for measuring sensor current output 50 pA to 3 mA range Programmable load and gain resistors for sensor output Analog hardware accelerators Digital waveform generator Receive filters Complex impedance measurement (DFT) engine 1 high speed TIA to handle wide bandwidth input signals from 0.015 Hz up to 200 kHz Digital waveform generator for generation of sinusoid and trapezoid waveforms 2.5 V and 1.82 V internal reference voltage sources System level power savings Fast power-up and power-down analog blocks for duty cycling Programmable AFE sequencer to minimize workload of host controller 6 kB SRAM to preprogram AFE sequences Ultra low power potentiostat channel: 6.5 µAof current consumption when powered on and all other blocks in hibernate mode Smart sensor synchronization and data collection Cycle accurate control of sensor measurement Sequencer controlled GPIOs On-chip peripherals SPI serial input/output Wake-up timer Interrupt controller Power 2.8 V to 3.6 V supply 1.82 V input/output compliant Power-on reset Hibernate mode with low power DAC and potentiostat amplifier powered up to maintain sensor bias Package and temperature range 3.6 mm × 4.2 mm, 56-ball WLCSP 7 mm × 7 mm, 48-lead LFCSP Fully specified for operating temperature range of −40°C to +85°C AD5940 and AD5941 fully specified for operating temperature range of −40°C to +85°C AD5941W fully specified for operating temperature range of −40°C to +105°C AEC-Q100 qualified for automotive applications

4-Channel, I2C, Ultralow Power 12-Bit ADC in 20-Lead LFCSP/TSSOP Features: I2C-compatible serial interface supports standard and fast modes Ultralow power: 90 μW typical at 3 V in fast mode Specified for VDD of 2.7 V to 5.25 V On-chip accurate 2.5 V reference, 5 ppm/°C typical drift 4 single-ended analog input channels ALERT function BUSY function Autocycle mode Wide input bandwidth 68 dB signal-to-noise ratio (SNR) typical at input frequency of 1 kHz Flexible power/throughput rate management No pipeline delays Power-down mode 550 nA typical at VDD = 5.25 V 435 nA typical at VDD = 3 V 20-lead LFCSP and TSSOP packages Temperature range: −40°C to +125°C

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs  Support for lane rates up to 16 Gbps per lane  1.65 W total power per channel at 3 GSPS (default settings)  Performance at −2 dBFS amplitude, 2.6 GHz input SFDR = 70 dBFS SNR = 57.2 dBFS Performance at −9 dBFS amplitude, 2.6 GHz input SFDR = 78 dBFS SNR = 59.5 dBFS Integrated input buffer Noise density = −152 dBFS/Hz 0.975 V, 1.9 V, and 2.5 V dc supply operation 9 GHz analog input full power bandwidth (−3 dB) Amplitude detect bits for efficient AGC implementation 2 integrated, wideband digital processors per channel 48-bit NCO  4 cascaded half-band filters  Phase coherent NCO switching Up to 4 channels available  Serial port control Integer clock with divide by 2 and divide by 4 options Flexible JESD204B lane configurations On-chip dither

14-Bit, 1300 MSPS/625 MSPS, JESD204B, Dual Analog-to-Digital Converter Features: JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps 1.6 W total power at 1300 MSPS 800 mW per ADC channel SNR = 65.6 dBFS at 172 MHz (1.59 VP-P input range) SFDR = 78 dBFS at 172.3 MHz (1.59 VP-P input range) Noise density −153.9 dBFS/Hz (1.59 VP-P input range) −155.6 dBFS/Hz (2.04 VP-P input range) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible input range 1.36 VP-P to 2.04 VP-P (1.59 VP-P typical) 2 GHz usable analog input full power bandwidth >95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated digital downconverters per ADC channel 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity