20 V, 6 A, Synchronous Step-Down DC-to-DC Regulator Features: Input voltage: 4.5 V to 20 V Integrated MOSFET: 44 m/11 m Reference voltage: 0.6 V ± 1% Continuous output current: 6 A Programmable switching frequency: 200 kHz to 1.4 MHz Synchronizes to external clock: 200 kHz to 1.4 MHz 180° out of phase clock synchronization Precision enable and power good External compensation Internal soft start with external adjustable option Startup into a precharged output Supported by ADIsimPower design tool

20 V, 6 A, Synchronous, Step-Down DC-to-DC Regulator Features: Input voltage range: 4.5 V to 20 V Integrated MOSFET: 44 mΩ typical/11 mΩ typical Reference voltage: 0.6 V ± 1% Continuous output current: 6 A Programmable current-limit thresholdProgrammable switching frequency: 200 kHz to 1400 kHz Precision enable and power good External compensation Internal soft start with external adjustable option Startup into a precharged output Supported by ADIsimPower design tool

18 V, 12 A Step-Down Regulator with Programmable Current Limit Features: Input voltage: 4.5 V to 18 V Continuous output current: 12 A Integrated MOSFETs: 17 mΩ high-side/4.5 mΩ low-side 0.6 V ± 0.5% reference voltage Programmable switching frequency range: 200 kHz to 2200 kHz Enhanced transient response Programmable current limit with ±10% accuracy Precision enable and power good External compensation and soft start Start up into a precharged output Supported by the ADIsimPower design tool

3 A, 36 V, Synchronous Step-Down DC-to-DC Regulator Features: Continuous output current: 3 A Input voltage: 4.5 V to 36 V Integrated MOSFETs: 98 mΩ/35 mΩ Reference voltage: 0.6 V ± 1% Fast minimum on time: 50 ns Programmable switching frequency: 200 kHz to 1.8 MHz Synchronizes to external clock: 200 kHz to 1.8 MHz Precision enable and power good Cycle-by-cycle current limit with hiccup protection External compensation Programmable soft start time Startup into a precharged output Supported by ADIsimPower design tool

600 mA, 2.5 MHz Buck-Boost DC-to-DC Converter Features: 1 mm height profile Compact PCB footprint Seamless transition between modes 38 μA typical quiescent current 2.5 MHz operation enables 1.5 μH inductor Input voltage: 2.3 V to 5.5 V Fixed output voltage: 2.8 V to 5.0 V See data sheet for additional features

Ultralow Power Energy Harvester PMU with MPPT and Charge Management Features: Boost regulator with maximum power point tracking (MPPT) with dynamic sensing or no sensing mode Hysteresis mode for best ultralight load efficiency Operating quiescent current of SYS pin (VIN > VCBP ≥ VMINOP): 510 nA Sleeping quiescent current of SYS pin (VCBP < VMINOP): 390 nA Input voltage operating range: 0.08 V to 3.3 V Fast cold start from 380 mV (typical) with charge pump Programmable shutdown point on MINOP pin based on the input open circuit voltage (OCV) 150 mA regulated output from 1.5 V to 3.6 V Battery terminal charging threshold (2.2 V to 5.2 V) to support charging storage elements Optional BACK_UP power path management Radio frequency (RF) transmission conducive to shutting down the switcher temporarily via microcontroller unit (MCU) communication

400 MHz TO 4000 MHz Low Noise Amplifier Features: Operation from 400 MHz to 4000 MHz Noise figure of 0.8 dB at 900 MHz Requires few external components Integrated active bias control circuit Integrated dc blocking capacitors Adjustable bias for low power applications Single-supply operation from 3 V to 5 V Gain of 20.8 dB at 900 MHz OIP3 of 37.0 dBm at 900 MHz P1dB of 21.8 dBm at 900 MHz Small footprint LFCSP Pin-compatible version with 21.5 dB gain available

DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch