The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.Applications Communications Diversity multi-band, multi-mode digital receivers 3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Radar Digital oscilloscopes High speed data acquisition systems DOCSIS CMTS upstream receive paths HFC digital reverse path receivers

The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The ?3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).The AD9689 is available in a Pb-free, 196-ball BGA, specified over the ?40?C to +85?C ambient temperature range. This product is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product Highlights Wide, input ?3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz. Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers. Fast NCO switching enabled through the GPIO pins. SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. On-chip temperature diode for system thermal management. 12 mm ? 12 mm, 196-ball BGA. Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.Applications Diversity multiband and multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A Electronic test and measurement systems Phased array radar and electronic warfare DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9714/AD9715/AD9716/AD9717 are pin-compatible, dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC? converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9714/AD9715/AD9716/AD9717 make them well-suited for portable and low power applications.PRODUCT HIGHLIGHTS Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 35 mW at 125 MSPS with a 1.8 V supply. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows easy interfacing to other components that accept common- mode levels greater than 0 V.?APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The LTC4126-ADJ is a low-power wireless single-cell Li-Ion battery charger with an integrated step-down DC/DC regulator. The step-down regulator is a low-noise multimode charge pump which is powered from the battery and provides a regulated 1.2V at the output. The switching frequency is set to either 50kHz or 75kHz depending on the mode to keep any switching noise out of the audible range.The constant-current constant-voltage Li-Ion battery charger has automatic recharge, automatic termination by safety timer, and battery temperature monitoring via an NTC pin. Charge current is programmable from 1mA to 50mA via an external resistor. Undervoltage protection disconnects the battery from all loads when the battery voltage is below 3.0V.The small package and minimal external component count make the LTC4126-ADJ and its variants suitable for hearing aid applications and other low power portable devices. See the chart in the data sheet.APPLICATIONSHearing AidsLow Power Li-Ion Powered DevicesWireless HeadsetsIoT Wearables

Demonstration circuit DC3082A-C features the LTM4681: the wide input and output voltage range, high efficiency and power density, high current PolyPhase® single output DC/DC step-down μModule® regulator with digital power system management. DC3082A-C is configured as 16-phase single output using 4× LTM4681. The factory default input voltage is 12V typical, output voltage is 1V at 480A typical or 500A peak with recommended 400LFM forced airflow. The demo board output voltages can be adjusted from 0.6V to 1V. Programming the output voltages to any value that is greater than 1V, requires derating output current based on thermal derating curves provided in the data sheet of the LTM4681. Heat sink or other appropriate electronic cooling systems can also be used in conjunction with forced airflow to further optimize the output power when the output is on and loaded with maximum output current. The factory default switching frequency is preset at 350kHz typical. DC3082A-C comes with PMBus interface and digital power system management functions. An onboard 12-pin connector is available for users to connect the dongle DC1613A to the demo board, provides an easy way to communicate and program the part using LTpowerPlay® software development tool. LTpowerPlay software and I2C/PMBus/SMBus dongle DC1613A allows users to monitor real time telemetry of input and output voltages, input and output current, switching frequency, internal IC die temperatures, power stage component temperatures and fault logs. Programmable parameters include device address, output voltages, control loop compensation, switching frequency, phase interleaving, DCM or CCM mode of operation, digital soft-start, sequencing and time based shutdown, fault responses to input and output overvoltage, output overcurrent, IC die and power component overtemperature. The LTM4681 is available in a thermally enhanced, low profile 330-Lead (15mm × 22mm × 8.17mm) BGA package. It is recommended to read the data sheet and the demo manual of LTM4681 prior to use or making any hardware changes to DC3082A-C. LTpowerPlay software can be downloaded here. USB to PMBus Controller Dongle DC1613A for use with LTpowerPlay is available here.

The LTC3307A is a very small, high efficiency, low noise, monolithic synchronous 3A step-down DC/DC converter operating from a 2.25V to 5.5V input supply. Using constant frequency, peak current mode control at switching frequencies 1MHz to 3MHz and minimum on-time as low as 22ns, this regulator achieves fast transient response with small external components. Silent Switcher architecture minimizes EMI emissions.The LTC3307A operates in forced continuous or pulse skip mode for low noise, or low-ripple Burst Mode operation for high efficiency at light loads, ideal for battery-powered systems. The IC regulates output voltages as low as 500mV. Other features include output overvoltage protection, short-circuit protection, thermal shutdown, clock synchronization, and up to 100% duty cycle operation for low dropout. The device is available in a low profile 12-lead 2mm ? 2mm ? 0.74mm LQFN package with exposed pad for low thermal resistance.APPLICATIONS Optical Networking, Servers, Telecom Automotive, Industrial, Communications Distributed DC Power Systems (POL) FPGA, ASIC, ?P Core Supplies Battery Operated Systems

Demonstration circuit 3162A is a 18V, 10A synchronous step-down Silent Switcher® with spread spectrum frequency modulation featuring the LT8642-1. The demo board is designed for 1.2V output from a 2.8V to 18V input. The LT8642-1 is a compact, low emission, high efficiency, and high speed synchronous monolithic stepdown switching regulator. Special Silent Switcher architecture minimizes EMI emissions. Selectable spread spectrum mode can further improve EMI performance. Fast minimum on-time of 20ns enables high VIN to low VOUT conversion at high frequency. The LT8642-1 switching frequency can be programmed either via a resistor or external clock over a 200kHz to 3MHz range. The default frequency of demo circuit 3162A is 2MHz. The LT8642-1 SYNC/MODE pin on the demo board is grounded (JP1 at BURST position) by default for low ripple Burst Mode® operation. Spread spectrum mode and forced continuous mode can be selected respectively by moving JP1 shunt. To synchronize to an external clock, move JP1 to FCM/SYNC and apply the external clock to the SYNC terminal. The LT8642-1 data sheet gives a complete description of the part, operation, and application information. The data sheet must be read in conjunction with this demo manual for demo circuit 3162A. The LT8642-1 is assembled in a 3mm × 4mm LQFN package with exposed pads for low thermal resistance. The layout recommendations for low EMI operation and maximum thermal performance are available in the data sheet section Low EMI PCB Layout and Thermal Considerations.

IC ROBUST QUAD ISO 4:0 CH ;ROHS COMPLIANT: YES

IC ROBUST QUAD ISO 4:0 CH ;ROHS COMPLIANT: YES