The HMC862A is a low noise, programmable frequency divider in a 3 mm × 3 mm, leadless, surface-mount package. The frequency divider, N, can be programmed to divide from 1, 2, 4, or 8 in the 0.1 GHz to 24 GHz input frequency range.The low phase noise, wide frequency range, and flexible division ratio make this device ideal for high performance and wideband communication systems.Applications Satellite communication systems Point to point and point to multipoint radios Military applications Test equipment

The HMC939ALP4E is a 5-bit digital attenuator with a 31 dBattenuation control range in 1 dB steps.The HMC939ALP4E offers optimum insertion loss, attenuationaccuracy, and input linearity over the specified frequency rangefrom 100 MHz to 33 GHz.The HMC939ALP4E requires dual supply voltages, VDD = +5 Vand VSS = −5 V, and provides CMOS-/TTL-compatible parallelcontrol interface by incorporating an on-chip driver.The HMC939ALP4E comes in a RoHS compliant, compact,4 mm × 4 mm LFCSP package. See HMC939A-DIE for the dieversion of HMC939ALP4E.Applications Test instrumentation Microwave radios and very small aperture terminals (VSATs) Military radios, radars, electronic counter measures (ECMs) Broadband telecommunications systems

The AD4001/AD4005 are high accuracy, high speed, low power, 16-bit, Easy Drive, precision successive approximation register (SAR) analog-to-digital converters (ADCs) that operate from a single power supply, VDD. The reference voltage, VREF, is applied externally and can be set independent of the supply voltage. The AD4001/AD4005 power scales linearly with throughput. Easy Drive features reduce both signal chain complexity and power consumption while enabling higher channel density. The reduced input current, particularly in high-Z mode, coupled with a long signal acquisition phase, eliminates the need for a dedicated ADC driver. Easy Drive broadens the range of companion circuitry that is capable of driving these ADCs (see Figure 2 in the data sheet).Input span compression eliminates the need to provide a negative supply to the ADC driver amplifier while preserving access to the full ADC code range. The input overvoltage clamp protects the ADC inputs against overvoltage events, minimizing disturbances on the reference pin and eliminating the need for external protection diodes. Fast device throughput up to 2 MSPS allows users to accurately capture high frequency signals and to implement oversampling techniques to alleviate the challenges associated with antialias filter designs. Decreased serial peripheral interface (SPI) clock rate requirements reduce digital input and output power consumption, broadens digital host options, and simplifies the task of sending data across digital isolation. The SPI-compatible serial user interface is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic by using the separate VIO logic supply.APPLICATIONS Automated test equipment Machine automation Medical equipment Battery-powered equipment Precision data acquisition systems Instrumentation and control systems

The AD5592R/AD5592R-1 have eight I/Ox pins (I/O0 to I/O7) that can be independently configured as digital-to-analog converter (DAC) outputs, analog-to-digital converter (ADC) inputs, digital outputs, or digital inputs. When an I/Ox pin is configured as an analog output, it is driven by a 12-bit DAC. The output range of the DAC is 0 V to VREF or 0 V to 2 × VREF. When an I/Ox pin is configured as an analog input, it is connected to a 12-bit ADC via an analog multiplexer. The input range of the ADC is 0 V to VREF or 0 V to 2 × VREF. The ADC has a total throughput rate of 400 kSPS. The I/Ox pins can also be configured as digital, general-purpose input or output (GPIO) pins. The state of the GPIO pins can be set or read back by accessing the GPIO write data register or the GPIO read configuration register, respectively, via a serial peripheral interface (SPI) write or read operation.The AD5592R/AD5592R-1 have an integrated 2.5 V, 20 ppm/°C reference, which is turned off by default, and an integrated temperature indicator, which gives an indication of the die temperature. The temperature value is read back as part of an ADC read sequence.The AD5592R/AD5592R-1 are available in 16-ball, 2 mm × 2 mm WLCSP, 16-lead, 3 mm × 3 mm LFCSP, and 16-lead TSSOP. The AD5592R/AD5592R-1 operate over a temperature range of −40 °C (TA) to +125 °C (TJ).APPLICATIONS Control and monitoring General-purpose analog and digital inputs/outputs

The AD5592R/AD5592R-1 have eight I/Ox pins (I/O0 to I/O7) that can be independently configured as digital-to-analog converter (DAC) outputs, analog-to-digital converter (ADC) inputs, digital outputs, or digital inputs. When an I/Ox pin is configured as an analog output, it is driven by a 12-bit DAC. The output range of the DAC is 0 V to VREF or 0 V to 2 × VREF. When an I/Ox pin is configured as an analog input, it is connected to a 12-bit ADC via an analog multiplexer. The input range of the ADC is 0 V to VREF or 0 V to 2 × VREF. The ADC has a total throughput rate of 400 kSPS. The I/Ox pins can also be configured as digital, general-purpose input or output (GPIO) pins. The state of the GPIO pins can be set or read back by accessing the GPIO write data register or the GPIO read configuration register, respectively, via a serial peripheral interface (SPI) write or read operation.The AD5592R/AD5592R-1 have an integrated 2.5 V, 20 ppm/°C reference, which is turned off by default, and an integrated temperature indicator, which gives an indication of the die temperature. The temperature value is read back as part of an ADC read sequence.The AD5592R/AD5592R-1 are available in 16-ball, 2 mm × 2 mm WLCSP, 16-lead, 3 mm × 3 mm LFCSP, and 16-lead TSSOP. The AD5592R/AD5592R-1 operate over a temperature range of −40 °C (TA) to +125 °C (TJ).APPLICATIONS Control and monitoring General-purpose analog and digital inputs/outputs

The AD5593R has eight input/output (I/O) pins, which can beindependently configured as digital-to-analog converter (DAC)outputs, analog-to-digital converter (ADC) inputs, digital outputs,or digital inputs. When an I/O pin is configured as an analogoutput, it is driven by a 12-bit DAC. The output range of theDAC is 0 V to VREF or 0 V to 2 × VREF. When an I/O pin isconfigured as an analog input, it is connected to a 12-bit ADCvia an analog multiplexer. The input range of the ADC is 0 V toVREF or 0 V to 2 × VREF. The I/O pins can also be configured tobe general-purpose, digital input or output (GPIO) pins. Thestate of the GPIO pins can be set or read back by accessing theGPIO write data register and GPIO read configuration registers,respectively, via an I2C write or read operation.The AD5593R has an integrated 2.5 V, 20 ppm/°C reference thatis turned off by default and an integrated temperature indicatorthat gives an indication of the die temperature. The temperaturevalue is read back as part of an ADC read sequence.The AD5593R is available in 16-lead TSSOP and LFCSP, as wellas a 16-ball WLCSP, and operates over a temperature range of−40°C to +105°C.APPLICATIONS Control and monitoring General-purpose analog and digital I/O

The AD5593R has eight input/output (I/O) pins, which can beindependently configured as digital-to-analog converter (DAC)outputs, analog-to-digital converter (ADC) inputs, digital outputs,or digital inputs. When an I/O pin is configured as an analogoutput, it is driven by a 12-bit DAC. The output range of theDAC is 0 V to VREF or 0 V to 2 × VREF. When an I/O pin isconfigured as an analog input, it is connected to a 12-bit ADCvia an analog multiplexer. The input range of the ADC is 0 V toVREF or 0 V to 2 × VREF. The I/O pins can also be configured tobe general-purpose, digital input or output (GPIO) pins. Thestate of the GPIO pins can be set or read back by accessing theGPIO write data register and GPIO read configuration registers,respectively, via an I2C write or read operation.The AD5593R has an integrated 2.5 V, 20 ppm/°C reference thatis turned off by default and an integrated temperature indicatorthat gives an indication of the die temperature. The temperaturevalue is read back as part of an ADC read sequence.The AD5593R is available in 16-lead TSSOP and LFCSP, as wellas a 16-ball WLCSP, and operates over a temperature range of−40°C to +105°C.APPLICATIONS Control and monitoring General-purpose analog and digital I/O

The AD5676 is a low power, octal, 16-bit buffered voltage output digital-to-analog converter (DAC). The device includes a gain select pin, giving a full-scale output of VREF (gain = 1) or 2 × VREF (gain = 2). The AD5676 DAC operates from a single 2.7 V to 5.5 V supply and is guaranteed monotonic by design. The AD5676 is available in 20-lead TSSOP and LFCSP packages.The internal power-on reset circuit and the RSTSEL pin of the AD5676 ensure that the output DACs power up to zero scale or midscale and then remain there until a valid write takes place. The AD5676 contains a per channel power-down mode that typically reduces the current consumption of the device to 1 µA.The AD5676 employs a versatile serial peripheral interface (SPI) that operates at clock rates up to 50 MHz, and contains a VLOGIC pin intended for 1.62 V to 5.5 V logic.Product Highlights High Relative Accuracy (INL) 16-bit: ±3 LSB maximum −40°C to +125°C temperature range 20-lead, TSSOP and LFCSP RoHS-compliant packagesApplications Optical transceivers Base-station power amplifiers Process control (PLC input/output cards) Industrial automation Data acquisition systems

The AD5761R/AD5721R are single channel, 16-/12-bit serialinput, voltage output, digital-to-analog converters (DACs).They operate from single supply voltages from +4.75 V to+30 V or dual supply voltages from −16.5 V to 0 V VSS and+4.75 V to +16.5 V VDD. The integrated output amplifier,reference buffer, and reference provide a very easy to use,universal solution.The devices offer guaranteed monotonicity, integral nonlinearity(INL) of ±2 LSB maximum, 35 nV/√Hz noise, and 7.5 μs settlingtime on selected ranges.The AD5761R/AD5721R use a serial interface that operates atclock rates of up to 50 MHz and are compatible with DSP andmicrocontroller interface standards. Double buffering allows theasynchronous updating of the DAC output. The input codingis user-selectable twos complement or straight binary. Theasynchronous reset function resets all registers to their defaultstate. The output range is user selectable, via the RA[2:0] bitsin the control register.The devices available in a 3 mm × 3 mm LFCSP package and a16-lead TSSOP package offer guaranteed specifications over the−40°C to +125°C industrial temperature range.Applications Industrial automation Instrumentation, data acquisition Open-/closed-loop servo control, process control Programmable logic controllers

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package. The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins. The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI. The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios