The AD9523-1 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO with two VCO dividers. The on-chip VCO tunes from 2.94 GHz to 3.1 GHz.The AD9523-1 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free, coarse timing adjustment in increments that are equal to half the period of the signal coming out of the VCO.An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

The 10 clock outputs of the AD9544 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.The AD9544 is available in a 48-lead LFCSP (7 mm ? 7 mm) package and operates over the ?40?C to +85?C temperature range.Note that throughout this data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.Appliations SyncE and GPS synchronization and jitter cleanup Optical transport networks (OTN), SDH, and macro and small cell base stations OTN mapping/demapping with jitter cleaning Small base station clocking, including baseband and radio Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking Cable infrastructures Carrier Ethernet

The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9559 operates over an industrial temperature range of ?40?C to +85?C. If a single DPLL version of this part is needed, refer to the AD9557.APPLICATIONS Network synchronization, including Synchronous Ethernet and OTN mapping/de-mapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF? and SYNCINB? input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the ?40?C to +85?C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm ? 9 mm, 64-lead LFCSP.APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers

The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.Applications Communications Diversity multi-band, multi-mode digital receivers 3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Radar Digital oscilloscopes High speed data acquisition systems DOCSIS CMTS upstream receive paths HFC digital reverse path receivers

The AD9714/AD9715/AD9716/AD9717 are pin-compatible, dual, 8-/10-/12-/14-bit, low power digital-to-analog converters (DACs) that provide a sample rate of 125 MSPS. These TxDAC? converters are optimized for the transmit signal path of communication systems. All the devices share the same interface, package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost.The AD9714/AD9715/AD9716/AD9717 offer exceptional ac and dc performance and support update rates up to 125 MSPS.The flexible power supply operating range of 1.8 V to 3.3 V and low power dissipation of the AD9714/AD9715/AD9716/AD9717 make them well-suited for portable and low power applications.PRODUCT HIGHLIGHTS Low Power. DACs operate on a single 1.8 V to 3.3 V supply; total power consumption reduces to 35 mW at 125 MSPS with a 1.8 V supply. Sleep and power-down modes are provided for low power idle periods. CMOS Clock Input. High speed, single-ended CMOS clock input supports a 125 MSPS conversion rate. Easy Interfacing to Other Components. Adjustable output common mode from 0 V to 1.2 V allows easy interfacing to other components that accept common- mode levels greater than 0 V.?APPLICATIONS Wireless infrastructures Picocell, femtocell base stations Medical instrumentation Ultrasound transducer excitation Portable instrumentation Signal generators, arbitrary waveform generators

The AD9910 is a direct digital synthesizer (DDS) featuringan integrated 14-bit DAC and supporting sample rates up to1 GSPS. The AD9910 employs an advanced, proprietary DDStechnology that provides a significant reduction in power consumptionwithout sacrificing performance. The DDS/DACcombination forms a digitally programmable, high frequency,analog output synthesizer capable of generating a frequencyagile sinusoidal waveform at frequencies up to 400 MHz.The user has access to the three signal control parameters thatcontrol the DDS: frequency, phase, and amplitude. The DDSprovides fast frequency hopping and frequency tuning resolutionwith its 32-bit accumulator. With a 1 GSPS sample rate, thetuning resolution is ~0.23 Hz. The DDS also enables fast phaseand amplitude switching capability.The AD9910 is controlled by programming its internal controlregisters via a serial I/O port. The AD9910 includes an integratedstatic RAM to support various combinations of frequency, phase,and/or amplitude modulation. The AD9910 also supports a userdefined, digitally controlled, digital ramp mode of operation. Inthis mode, the frequency, phase, or amplitude can be variedlinearly over time. For more advanced modulation functions, ahigh speed parallel data input port is included to enable directfrequency, phase, amplitude, or polar modulation.The AD9910 is specified to operate over the extended industrialtemperature range.Applications Agile local oscillator (LO) frequency synthesis Programmable clock generators FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulators Fast frequency hopping

The AD9912 is a direct digital synthesizer (DDS) that features an integrated 14-bit digital-to-analog converter (DAC). The AD9912 features a 48-bit frequency tuning word (FTW) that can synthesize frequencies in step sizes no larger than 4 ?Hz. Absolute frequency accuracy can be achieved by adjusting the DAC system clock.The AD9912 also features an integrated system clock phase-locked loop (PLL) that allows for system clock inputs as low as 25 MHz.The AD9912 operates over an industrial temperature range, spanning ?40?C to +85?C.APPLICATIONS Agile LO frequency synthesis Low jitter, fine tune clock generation Test and measurement equipment Wireless base stations and controllers Secure communications Fast frequency hopping

The AD9988 is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The device supports four transmitter channels and four receiver channels with a 4T4R configuration. This product is well suited for four-antenna TDD transmitter applications, where the receiver path can be shared between receiver and observation modes. The GPIO pins can be configured and toggled to support different user modes, while phase coherency is maintained. The maximum radio channel bandwidth supported is 1.2 GHz in a 4T4R configuration and a sample resolution of 16 bits. The AD9988 features a 16-lane 24.75 Gbps JESD204C or 15.5 Gbps JESD204B serial data port that allows up to eight lanes per transmit/receive link, an on-chip clock multiplier, and digital signal processing capability targeted at multiband direct to RF radio applications.APPLICATIONSWireless communications infrastructureW-CDMA, LTE, LTE-A, massive multiple input multiple output (MIMO)Point to point microwave, E-band, and 5G mmWaveBroadband communications systemsDOCSIS 3.0+ cable modem termination system (CMTS)Communication test and measurement systems

The EV-21593-SOM enables evaluation and rapid prototyping of designs featuring the ADSP-2159x Family (ADSP-21591/ADSP-21593) of SHARC audio processors. It provides an easy-to-use plug-n-play reference design with expansion capabilities to interface to custom hardware ahead of the release of the processor itself. When the EV-21593-SOM board is plugged into the EV-SOMCRR-EZKIT carrier board, the resulting EZ-KIT® evaluation system (EV-21593-EZKIT) can be used for fast and easy evaluation of the processor core and system peripherals/interfaces. The EV-21593-SOM enables rapid prototyping for a wide range of applications, including immersive 3D sound and personal audio zones (PAZ), automotive active and road noise cancellation (ANC/RNC), voice-based user-interfaces and in-car communications (ICC), engine sound synthesis (ESS) and electric vehicle warning sound systems (EVWSS/AVAS). Additional applications include professional audio and soundbars / home AVRs (with 3D Object and Multi-Channel Audio) and enhanced conferencing systems. ADI offers several software modules (e.g., AEC/NR, microphone beamforming, pitch shifting, harmonic generators, wave players etc.), as well as complete software solutions that can be licensed, where users can develop/evaluate their audio and voice processing applications. ADI also offers 3rd party surround sound solutions that can be licensed on ADI’s SHARC processor families. Please visit ADI’s Software Solutions page for more information. The EV-21593-SOM module utilizes the CrossCore® Embedded Studio (CCES) development tools to enable developers to achieve faster time to market. The development environment aids advanced application code development and debug, such as: Create, compile, assemble, and link application programs written in C++, C, and assembly Load, run, step, halt, and set breakpoints in application programs Read and write data and program memory Read and write core and peripheral registers