Silicon SPDT Switch, Nonreflective, 100 MHz to 44 GHz Features: Ultrawideband frequency range: 100 MHz to 44 GHz Nonreflective design Low insertion loss: 1.2 dB to 18 GHz 1.7 dB to 26 GHz 2.4 dB to 40 GHz 3.8 dB to 44 GHz High isolation 55 dB to 18 GHz 53 dB to 26 GHz 50 dB to 40 GHz 45 dB to 44 GHz High input linearity P1dB: 27 dBm typical IP3: 53 dBm typical High power handling 24 dBm insertion loss path 24 dBm isolation path All off state control No low frequency spurious signals 0.1 dB RF settling time: 40 ns typical 20-terminal, 3 mm × 3 mm LGA package Pin compatible with ADRF5027, low frequency cutoff versionADRF5026-EP supports defense and aerospace applications (AQEC standard) Download ADRF5026-EP data sheet (pdf) Supports defense and aerospace applications (AQEC standard) Military temperature range (−55°C to +105°C) Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/21601 DSCC Drawing Number

Nonreflective, 9 kHz to 44 GHz Silicon SP4T Switch Features: Ultrawideband frequency range: 9 kHz to 44 GHz Nonreflective 50 Ω design Low insertion loss: 1.5 dB at 18 GHz 2.4 dB at 40 GHz 2.5 dB at 44 GHz High isolation: 44 dB at 18 GHz 39 dB at 40 GHz 36 dB at 44 GHz High input linearity: P0.1dB: 26 dBm typical IP3: 48 dBm typical High power handling 24 dBm through path 24 dBm terminated path All off state control Logic select control No low frequency spurs Settling time (0.1 dB final RF output): 6 μs 24-terminal, 3 mm × 3 mm LGA package Pin compatible with ADRF5042, fast switching version

Triple-Channel, Digital Isolator, Enhanced System-Level ESD Reliability (2/1 channel directionality) Features: Enhanced system-level ESD performance per IEC 61000-4-x Low power operation 5 V operation 2.0 mA per channel maximum at 0 Mbps to 2 Mbps 4.1 mA per channel maximum at 10 Mbps 36 mA per channel maximum at 90 Mbps 3.3 V operation 1.0 mA per channel maximum at 0 Mbps to 2 Mbps 2.8 mA per channel maximum at 10 Mbps 17 mA per channel maximum at 90 Mbps Bidirectional communication 3.3 V/5 V level translation High temperature operation: 105°C High data rate: dc to 90 Mbps (NRZ) Precise timing characteristics 2 ns maximum pulse width distortion 2 ns maximum channel-to-channel matching High common-mode transient immunity: >25 kV/μs Output enable function 16-lead SOIC wide body, RoHS-compliant package Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak CQC Certification per GB4943.1-2011

Small, 3.75 kV RMS Quad Digital Isolators (4/0 Channel Directionality) Features: Up to 25 Mbps data rate (NRZ) Low propagation delay: 25 ns typical Low dynamic power consumption 1.8 V to 5 V level translation High common-mode transient immunity: >25 kV/µs Output default select 20-lead, RoHS-compliant, SSOP package See data sheet for additional features

5 KV rms Isolated Precision Half-Bridge Driver, 4 A Output Features: 4 A peak output current Working voltage High-side or low-side relative to input: 537 V peak High-side to low-side differential: 800 V peak High frequency operation: 1 MHz maximum  3.3 V to 5 V CMOS input logic 4.5 V to 18 V output drive  UVLO at 2.5 V VDD1 ADuM3223A/ADuM4223A UVLO at 4.1 V VDD2 ADuM3223B/ADuM4223B UVLO at 7.0 V VDD2 ADuM3223C/ADuM4223C UVLO at 11.0 V VDD2 Precise timing characteristics  54 ns maximum isolator and driver propagation delay 5 ns maximum channel-to-channel matching CMOS input logic levels  High common-mode transient immunity:>25 kV/μs Enhanced system-level ESD performance per IEC 61000-4-x  High junction temperature operation: 125°C  Thermal shutdown protection  Default low output Safety and regulatory approvals ADuM4223 wide-body, 16-lead SOIC UL recognition per UL 1577  5000 V rms for 1 minute SOIC long package  CSA Component Acceptance Notice 5A  VDE certificate of conformity  DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak  Qualified for automotive applications

8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 8 differential/15 pseudo differential inputs See data sheet for additional features

Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Features: Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock See data sheet for additional features

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter Features:JESD204B (Subclass 1 and Subclass 0) coded serial digital outputs Lane rates up to 15 Gbps 1.6 W total power at 1 GSPS 400 mW per ADC channel SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range) SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range) SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range) 0.9 V, 1.8 V, and 2.5 V dc supply operation No missing codes Internal ADC voltage reference Analog input buffer On-chip dithering to improve small signal linearityFlexible differential input range 1.44 V p-p to 2.16 V p-p (1.44 V p-p default) 1.4 GHz analog input full power bandwidth Fast detect bits for efficient AGC implementation Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations

Single-Supply, Low Power, Precision FET Input Quad Buffer Features: Low power 250 μA maximum supply current per amplifier FET input 2 pA maximum input bias current at 25°C Extremely high input impedance Low noise 13 nV/√Hz voltage noise at 1 kHz 0.4 μV p-p voltage noise (0.1 Hz to 10 Hz) 0.8 fA/√Hz current noise at 1 kHz High dc precision 3 μV/°C maximum offset drift (B grade) 3 MHz bandwidth Unique pinout No leakage from inputs to supply pins Provides guarding capability Rail-to-rail output Single-supply operation Input range extends to ground Wide supply range Single-supply: 3 V to 36 V Dual-supply: ±1.5 V to ±18 V  Available in a compact 10-lead MSOP