The SHARC ADSP-21489 is one of two new members of the fourth generation of SHARC® Processors that now includes the ADSP-21483, ADSP-21486, ADSP-21487, ADSP-21488, ADSP-21489 and offers increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and new memory configurations capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21489 offers the highest performance–450 MHz/2700 MFLOPs–in an LQFP package within the fourth generation SHARC Processor family. This level of performance makes the ADSP-21489 particularly well suited to address the automotive audio and industrial control segments. In addition to its high core performance, the ADSP-21489 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.Fourth-generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, IDP, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as SPI,UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).

The HMC574AMS8E is low-cost SPDT switchin 8-lead MSOP packages for use in transmit/receive applications which requires very lowdistortion at high incident power levels. Thedevice can control signals from DC to 3 GHz andis especially suited for Cellular/3G infrastructure,WiMAX and WiBro applications with only 0.3 dBtypical insertion loss. The design provides 5 wattpower handling performance and +63 dBm thirdorder intercept at +8 Volt bias. RF1 and RF2 arereflective shorts when ?Off.?Applications Cellular/3G infrastructure Private mobile radio handsets WLAN, WiMAX and WiBro Automotive telematics Test equipment

The AD7476 / AD7477 / AD7478 are, respectively, 12-bit, 10-bit, and 8-bit, high speed, low power, successive approximation ADCs. The parts operate from a single 2.35 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. Each part contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 6 MHz.The conversion process and data acquisition are controlled using CS the serial clock, allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and the conversion is initiated at this point. There are no pipeline delays associated with these parts.The AD7476 / AD7477 / AD7478 use advanced design techniques to achieve very low power dissipation at high throughput rates. The reference for the parts is taken internally from VDD. This allows the widest dynamic input range to the ADC. Thus, the analog input range for the parts are 0 V to VDD. The conversion rate is determined by the SCLK.PRODUCT HIGHLIGHTS First 12-/10-/8-Bit ADCs in SOT-23 Packages. High Throughput with Low Power Consumption. Flexible Power/Serial Clock Speed Management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. This allows the average power consumption to be reduced while not converting. The parts also feature a shutdown mode to maximize power efficiency at lower throughput rates. Current consumption is 1 μA maximum when in shutdown mode. Reference Derived from the Power Supply. No Pipeline Delay. The parts feature a standard successive-approximation ADC with accurate control of the sampling instant via a CS input and once-off conversion control.APPLICATIONS Battery-powered systems Personal digital assistants Medical instruments Mobile communications Instrumentation and control systems Data acquisition systems High speed modems Optical sensors

Demonstration circuit 3033A is a triple output synchronous step-up/dual step-down supply featuring the LTC7817. The demonstration circuit is designed for two buck outputs 5V/10A, 3.3V/10A supplied by a boosted 10V output. Benefiting from this feature, the buck outputs are able to maintain regulation over a wide input voltage range of 4.5V to 36V which is suitable for automotive or other battery fed applications. Also, the demonstration circuit uses a drop-in layout whereas the main buck circuit components fit in an area of ¾-inch by 1½-inch, while the main boost circuit area is ¾-inch by 1¾-inch. The package style for the LTC7817 is a 38-pin exposed pad QFN. The main features of the board include rail tracking (buck channels only), an internal 5V linear regulator for bias, separated RUN pins for each output, a PGOOD signal (CH1 only), and a mode selector that allow the converter to run in forced continuous mode (FCM), pulse-skipping (PSM) or Burst Mode® operation (BURST). Synchronization to an external clock is also possible. The LTC7817 data sheet gives a complete description of these parts, operation and application information. The data sheet must be read in conjunction with this quick start guide for demo circuit 3033A.

Dual Channel, 16-Bit, 16 MUPS, Multispan, Multi-IO SPI DAC Features: 16-bit resolution 16 MUPS single channel rate in fast mode 11 MUPS single channel rate in precision mode 78 ns small signal settling time to 0.1% accuracy 100 ns large signal settling time to 0.1% accuracy Ultrasmall glitch: <50 pV×s Ultralow latency: 5 ns THD: −105 dB at 1 kHz Highly configurable output voltage span and offset 1.2 V and 1.8 V logic level compatible Single (classic) and dual SPI modes Multiple error detectors, both analog and digital domains 2.5 V internal voltage reference, 10 ppm/°C maximum temperature coefficient Small package: 4 mm × 4 mm LFCSP

Very Low Noise, Low Distortion Active RC Quad Universal Filter Features: Continuous Time—No Clock Four 2nd Order Filter Sections, 20kHz to 300kHz Center Frequency Butterworth, Chebyshev, Elliptic or Equiripple Delay Response Lowpass, Bandpass, Highpass Responses 99dB Typical S/N, ±5V Supply (Q = 1) 93dB Typical S/N, Single 5V Supply (Q = 1) Rail-to-Rail Input and Output Voltages DC Accurate to 3mV (Typ) ±0.5% Typical Center Frequency Accuracy “Zero-Power” Shutdown Mode Single or Dual Supply, 5V to 10V Total Resistor-Programmable fO, Q, Gain

ISOLATORS;

SIGNAL CONDITIONING ANALOG DEVE KITS;

IC ADC 14BIT 1.25MSPS 44MQFP; Resolution (Bits):14bit; Sampling Rate:1.25MSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; ADC / DAC Case Style:MQFP; No. of Pins:44Pins; Input Channel Type:Differential Single Ended; Data Interface:Parallel; Operating Temperature Min:-40°C; Operating Temperature Max:85°C; Packaging:Each; Product Range:Single 14-Bit Pipelined ADCs; Automotive Qualification Standard:-; MSL:MSL 3 - 168 hours; SVHC:No SVHC (20-Jun-2016); Supply Current:10mA; Supply Voltage Range:4.75V to 5.25V

Demo circuit 1560A is an isolated flyback μModule® DC/DC converter with LDO post regulator featuring LTM8048. The demo circuit is designed for a 6V flyback output and a 5V post regulator output from a 4.5V to 30V input. The typical current capability of the 6V flyback output varies with input voltage from about 110mA at VIN = 4.5V to about 370mA at VIN = 30V. The circuit provides 725VDC isolation.