5.6 GHz to 8.6 GHz, GaAs, MMIC, I/Q Downconverter Features: Conversion gain: 13 dB typical Image rejection: 32 dBc typical Input P1dB compression: −6 dBm typical Input IP3: 3 dBm typical, 6.0 GHz to 8.6 GHz Noise figure: 2 dB typical LO to RF isolation: 48 dBm typical LO to IF isolation: 13 dBm typical RF to IF isolation: 10 dBm typical Amplitude balance: 0.2 dB typical Phase balance: −2° typical RF return loss: 10 dB typical LO return loss: 15 dB typical IF return loss: 15 dB typical Exposed paddle, 4 mm × 4 mm, 24-lead, LFCSP

Dual 5V, 2A Synchronous Step-Down DC/DCs in Tiny LQFN and WLCSP Features: Dual Outputs Each with 2A Output Current High Efficiency: 19mΩ NMOS and 75mΩ PMOS Wide Bandwidth, Fast Transient Response Switching Frequency Synchronizable Up to 3MHz VIN Range: 2.25V to 5.5V VOUT Range: 0.5V to VIN VOUT Accuracy: ±1% Low Ripple Burst Mode® Operation Peak Current Mode Control Minimum On-Time: 25ns Safely Tolerates Inductor Saturation in Overload Shutdown Current: 1.2µA Precision 400mV Enable Thresholds Internal Soft-Start and Compensation Power Good Output Low Profile, Thermally Enhanced 12-Lead 2mm × 2mm × 0.74mm LQFN and 16-Ball 1.64mm × 1.64mm × 0.5mm WLCSP Packages AEC-Q100 Qualified for Automotive Applications

8-Bit, 1 GSPS, JESD204B, Quad Analog-to-Digital Converter Features:JESD204B (Subclass 1 and Subclass 0) coded serial digital outputs Lane rates up to 15 Gbps 1.6 W total power at 1 GSPS 400 mW per ADC channel SFDR: 71 dBFS at 611 MHz (1.44 V p-p input range) SNR: 48.6 dBFS at 611 MHz (1.44 V p-p input range) SINAD: 48.5 dBFS at 611 MHz (1.44 V p-p input range) 0.9 V, 1.8 V, and 2.5 V dc supply operation No missing codes Internal ADC voltage reference Analog input buffer On-chip dithering to improve small signal linearityFlexible differential input range 1.44 V p-p to 2.16 V p-p (1.44 V p-p default) 1.4 GHz analog input full power bandwidth Fast detect bits for efficient AGC implementation Differential clock input Integer clock divide by 1, 2, 4, or 8 On-chip temperature diode Flexible JESD204B lane configurations

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

Ultralow Power Energy Harvester PMU with MPPT and Charge Management Features: Boost regulator with maximum power point tracking (MPPT) with dynamic sensing or no sensing mode Hysteresis mode for best ultralight load efficiency Operating quiescent current of SYS pin (VIN > VCBP ≥ VMINOP): 510 nA Sleeping quiescent current of SYS pin (VCBP < VMINOP): 390 nA Input voltage operating range: 0.08 V to 3.3 V Fast cold start from 380 mV (typical) with charge pump Programmable shutdown point on MINOP pin based on the input open circuit voltage (OCV) 150 mA regulated output from 1.5 V to 3.6 V Battery terminal charging threshold (2.2 V to 5.2 V) to support charging storage elements Optional BACK_UP power path management Radio frequency (RF) transmission conducive to shutting down the switcher temporarily via microcontroller unit (MCU) communication

50 mA/500 mA, High Efficiency, Ultralow Power Step-Down Regulator Features: Input start-up voltage range: 2.15 V to 6.50 V Operates down to 2.00 V voltage Ultralow 180 nA quiescent current with no load Selectable output voltage of 1.2 V to 3.6V or 0.8V to 5.0V ±1.5% output accuracy over full temperature range in PWM mode Selectable hysteresis mode or PWM operation mode Output current Up to 50 mA in hysteresis mode Up to 500 mA in PWM mode VOUTOK flag monitors the output voltage 100% duty cycle operation mode 2 MHz switching frequency with optional synchronization input from 1.5 MHz to 2.5 MHz QOD option UVLO, OCP, and TSD protection 9-ball, 1.65 mm × 1.87 mm WLCSP −40°C to +125°C junction temperature

20 V, 200 mA, Low Noise, CMOS LDO Linear Regulator Features: Low noise: 11 μV rms independent of fixed output voltage   PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz, VOUT = 5 V, VIN = 7 V Input voltage range: 2.7 V to 20 V  Maximum output current: 200 mA  Initial accuracy: ±0.8% Accuracy over line, load, and temperature ±1.8%, TJ = −40°C to +125°C Low dropout voltage: 200 mV (typical) at a 200 mA load, VOUT = 5 V User-programmable soft start Low quiescent current, IGND = 50 μA (typical) with no load  Low shutdown current 1.8 μA at VIN = 5 V 3.0 μA at VIN = 20 V  Stable with a small 2.2 μF ceramic output capacitor  Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V 15 standard voltages between 1.2 V and 5.0 V are available Adjustable output from 1.2 V to VIN – VDO, output can be adjusted above initial set point   Precision enable  1 mm × 1.2 mm, 6-ball WLCSP 

2 A, Ultralow Noise, High PSRR, Adjustable Output, RF Linear Regulator Features: Input voltage range: 2.3 V to 5.5 V Adjustable output voltage range (VOUT): 1.2 V to 3.3 V Maximum load current: 2 A Low noise 0.9 μV rms total integrated noise from 100 Hz to 100 kHz 1.6 μV rms total integrated noise from 10 Hz to 100 kHz Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz Power supply rejection ratio (PSRR) 68 dB from 1 kHz to 100 kHz 45 dB at 1 MHz Dropout voltage: 200 mV typical at IOUT = 2 A, VOUT = 3.3 V Initial accuracy: ±0.6% at ILOAD = 10 mA Accuracy over line, load, and temperature: ±1.5% See data sheet for additional features

18 GHz to 44 GHz, GaAs, pHEMT, MMIC, 1/2 W Power Amplifier Features: Output P1dB: 29 dBm PSAT: 29.5 dBm Gain: 23.5 dB Output IP3: 38 dBm Supply voltage: 5 V at 800 mA Integrated power detector 50 Ω matched input/output Die size: 2.750 mm × 1.805 mm × 0.102 mm

18 GHz to 44 GHz, GaAs, pHEMT, MMIC, 1/2 W Power Amplifier Features: Output P1dB: 29 dBm PSAT: 29.5 dBm Gain: 23.5 dB Output IP3: 38 dBm Supply voltage: 5 V at 800 mA Integrated power detector 50 Ω matched input/output Die size: 2.750 mm × 1.805 mm × 0.102 mm