SPECIAL FUNCTION IC ROHS COMPLIANT: YES

Low IQ Boost/SEPIC/Inverting Converter with 1.5A, 150V Switch Features: Wide Input Voltage Range: 2.8V to 60V Ultralow Quiescent Current and Low Ripple Burst Mode® Operation: IQ = 9µA 1.5A, 150V Power Switch Positive or Negative Output Voltage Programming with a Single Feedback Pin Programmable Frequency (100kHz to 500kHz) Synchronizable to an External Clock Spread Spectrum Frequency Modulation for Low EMI BIAS Pin for Higher Efficiency Programmable Undervoltage Lockout (UVLO) Thermally Enhanced 16-lead MSOP Package AEC-Q100 Qualified for Automotive Applications

DA CONVERTOR;

60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller Features: Wide VIN Range: 4.5V to 60V (65V Abs Max) Wide Output Voltage Range: 0.8V ≤ VOUT ≤ 99% • VIN Adjustable Gate Drive Level 5V to 10V (OPTI-DRIVE) No External Bootstrap Diodes Required Low Operating IQ: 29μA (One Channel On) Selectable Gate Drive UVLO Thresholds Out-of-Phase Operation Reduces Required Input Capacitance and Power Supply Induced Noise Phase-Lockable Frequency: 75kHz to 850kHz Selectable Continuous, Pulse Skipping or Low Ripple Burst Mode® Operation at Light Loads Selectable Current Limit (LTC3892/LTC3892-2) Very Low Dropout Operation: 99% Duty Cycle Power Good Output Voltage Monitors (LTC3892/LTC3892-2) Low Shutdown IQ: 3.6μA Small 32-Lead 5mm × 5mm QFN Package (LTC3892/LTC3892-2) or TSSOP Package (LTC3892-1)

VCO Oscillators VCO SMT w/Buffer amp, 2.6 - 2.8 GHz

RF AMPLIFIERS ROHS COMPLIANT: YES

Ultralow Noise, 150 mA CMOS Linear Regulator Features: Chinese data sheet available Ultralow noise: 9 μV rms, independent of VOUT No additional noise bypass capacitor required Stable with 1 μF ceramic input and output capacitors Maximum output current: 150 mA Input voltage range: 2.2 V to 5.5 V Low quiescent current IGND = 10 μA with zero load Low shutdown current: <1 μA Low dropout voltage: 105 mV at 150 mA load Initial output voltage accuracy: ±1% Up to 14 fixed output voltage options: 1.8 V to 3.3 V PSRR performance of 70 dB at 10 kHz Current limit and thermal overload protection Logic-controlled enable 5-lead TSOT package 4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP AEC-Q100 qualified for automotive applications

OP AMP, 120MHZ, 190V/US, SC-70; No. of Amplifiers: 1 Amplifier; Bandwidth: 120MHz; Slew Rate: 190V/µs; Supply Voltage Range: 2.7V to 10V; Amplifier Case Style: SC-70; No. of Pins: 6Pins; Operating Temperature Min: -40°C; Operating Temperature Max: 125°C; Product Range: -; Automotive Qualification Standard: -; RoHS Phthalates Compliant: Yes; MSL: MSL 1 - Unlimited; SVHC: No SVHC (07-Jul-2017)

The AD8017 is a low cost, high output current dual op amp optimized to run on a +12 V power supply. Available in a thermally enhanced 8 lead SOIC package, the AD8017 is optimized for driving the CPE end of the xDSL line, particularly for PC based modem designs. Novel circuit design enables each amplifier in the dual AD8017 to deliver 10 V pk-to-pk output voltage and more than 200 mA typical output current.Breakthrough two stage current gain design on a high speed bipolar process technology means that the AD8017 can deliver low distortion output voltages to within 1 V of the power supply rail. The AD8017 consumes only 7 mA/Amp, setting the standard in high efficiency.An evaluation board is available for this product and may be ordered using the following product number: AD8017AR-EVAL.Lead free package option available (AD8017ARZ, AD8017ARZ-REEL).

The AD6684 is a 135 MHz bandwidth, quad intermediate frequency (IF) receiver. It consists of four 14-bit, 500 MSPS ADCs and various digital processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed to support communications applications. The analog full power bandwidth of the device is 1.4 GHz. The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD6684 is optimized for wide input bandwidth, excellent linearity, and low power in a small package. The analog inputs and clock signal input are differential. Each pair of ADC data outputs are internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters. Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6684 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining a 9-bit output resolution. Each ADC output is also connected internally to a VDR block. This optional mode allows full dynamic range for defined input signals. Inputs that are within a defined mask (based on DPD applications) are passed unaltered. Inputs that violate this defined mask result in the reduction of the output resolution. With VDR, the dynamic range of the observation receiver is determined by a defined input frequency mask. For signals falling within the mask, the outputs are presented at the maximum resolution allowed. For signals exceeding defined power levels within this frequency mask, the output resolution is truncated. This mask is based on DPD applications andsupports tunable real IF sampling, and zero IF or complex IF receive architectures. Operation of the AD6684 in the DDC, NSR, and VDR modes is selectable via SPI-programmable profiles (the default mode is NSR at startup).In addition to the DDC blocks, the AD6684 has several functions that simplify the AGC function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure each pair of IF receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins. The AD6684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI. The AD6684 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range. Product Highlights Low power consumption per channel. JESD204B lane rate support up to 15 Gbps. Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management.Applications Communications Diversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-A HFC digital reverse path receivers Digital predistortion observation paths General-purpose software radios