DC to 9 GHz, Vector Signal Generator Features: DC-coupled, 50 matched output Up to 4.3 dBm output power, 9.5 dBm at 9 GHz DAC core update rate: 12.0 GSPS (guaranteed minimum) in 2 NRZ mode Wide analog bandwidth DC to 9.0 GHz in 2 NRZ mode (12.0 GSPS DAC update rate) 1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate) DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate) Power dissipation of 4.88 W in 2 NRZ mode (10 GSPS DAC update rate) Bypassable datapath interpolation 2, 3, 4, 6, 8, 12, 16, 24 Instantaneous (complex) signal bandwidth 2.25 GHz with device clock at 5 GHz (2 interpolation) 1.8 GHz with device clock at 6 GHz (3 interpolation) Fast frequency hopping Integrated biCMOS buffer amplifier

Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 1.54 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.55 W at 12 GSPS, dual channel mode 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers Features: Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84GHz, −7 dBFS/tone RF output SFDR <−80 dBc at 1.84 GHz, −7 dBFS RF output Flexible 8-lane, 15.4 Gbps JESD204B interface Supports single-band and multiband use cases Supports 12-bit high density mode for increased data throughput Multiple chip synchronization Supports JESD204B Subclass 1 Selectable interpolation filter for a complete set of input data rates 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz Transmit enable function allows extra power saving and downstream circuitry protection High performance, low noise PLL clock multiplier Supports 12.6 GSPS DAC update rate Observation ADC clock driver with selectable divide ratios Low power 2.54 W with 2 DACs at 12 GSPS, DAC PLL on 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal lid, 0.80 mm pitch

Cascadable Super Sequencer with Margin Control and Fault Recording Features: Complete supervisory and sequencing solution for up to 17 supplies Expandable to 257 supplies with additional ADM1266 ICs connected to the 2-wire interdevice bus Fully programmable sequencing engine 17 supply fault detectors enable real time supervision of supplies 0.4 V to 15 V on VH1 to VH4 (VHx) 0.4 V to 5 V on VP1 to VP13 (VPx) Device powered by the higher of VH1 and VH2 inputs for improved operating redundancy 12-bit ADC for readback of all supervised voltages Black box nonvolatile fault recording 16 PDIOs 9 GPIOs 9 voltage output 8-bit DACs allow voltage margining adjustment via dc-to-dc converter trim/feedback node Main and backup memory Industry standard PMBus interface compliant Available in a 9 mm × 9 mm, 64-lead package

High Voltage Input Protection Device Features: Controls supply voltages from 4 V to 60 V Gate drive for low voltage drop reverse supply protection Gate drive for P-channel FETs Inrush current limiting control Adjustable current limit Foldback current limiting Automatic retry or latch-off on current fault Programmable current-limit timer for safe operating area (SOA) Power-good and fault outputs Analog undervoltage (UV) and overvoltage (OV) protection 16-lead, 3 mm × 3 mm LFCSP 16-lead QSOP

High Voltage Input Protection Device Features: Controls supply voltages from 4 V to 60 V Gate drive for low voltage drop reverse supply protection Gate drive for P-channel FETs Inrush current limiting control Adjustable current limit Foldback current limiting Automatic retry or latch-off on current fault Programmable current-limit timer for safe operating area (SOA) Power-good and fault outputs Analog undervoltage (UV) and overvoltage (OV) protection 16-lead, 3 mm × 3 mm LFCSP 16-lead QSOP

3 kV RMS Signal and Power Isolated RS-485 Transceiver with 15 kV IEC ESD Features: 3 kV rms isolated RS-485/RS-422 transceiver Low radiated emissions, integrated, isolated dc-to-dc converter Passes EN 55032 Class B with margin on a 2-layer PCB Cable invert smart feature Correct reversed cable connection on A, B, Y, and Z bus pins while maintaining full receiver fail-safe feature ESD protection on RS-485 A, B, Y and Z pins ≥±12 kV IEC61000-4-2 contact discharge ≥±15 kV IEC61000-4-2 air discharge High speed 25 Mbps data rate (ADM2565E/ADM2567E) Low speed 500 kbps data rate for EMI control (ADM2561E/ADM2563E) Flexible power supplies Input VCC supply of 3 V to 5.5 V Logic VIO supply of 1.7 V to 5.5 V VSEL pin to select VISO supply of 5 V (VCC > 4.5 V) or 3.3 V PROFIBUS compliant for 5 V VISO Wide operating temperature range: −40°C to +105°C High common-mode transient immunity: 250 kV/µs Short-circuit, open-circuit, and floating input receiver fail-safe Supports 196 bus nodes (72 kΩ receiver input impedance) Full hot swap support (glitch free power-up/power-down) Safety and regulatory approvals (pending) CSA Component Acceptance Notice 5A, DIN V VDE V 0884-11, UL 1577, CQC11-471543-2012, IEC 61010-1 Complies with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E) 28-lead, fine pitch SOIC_W package (10.15 mm 10.05 mm) with >8.0 mm creepage and clearance

3 kV RMS Signal and Power Isolated RS-485 Transceiver with 15 kV IEC ESD Features: 3 kV rms isolated RS-485/RS-422 transceiver Low radiated emissions, integrated, isolated dc-to-dc converter Passes EN 55032 Class B with margin on a 2-layer PCB Cable invert smart feature Correct reversed cable connection on A, B, Y, and Z bus pins while maintaining full receiver fail-safe feature ESD protection on RS-485 A, B, Y and Z pins ≥±12 kV IEC61000-4-2 contact discharge ≥±15 kV IEC61000-4-2 air discharge High speed 25 Mbps data rate (ADM2565E/ADM2567E) Low speed 500 kbps data rate for EMI control (ADM2561E/ADM2563E) Flexible power supplies Input VCC supply of 3 V to 5.5 V Logic VIO supply of 1.7 V to 5.5 V VSEL pin to select VISO supply of 5 V (VCC > 4.5 V) or 3.3 V PROFIBUS compliant for 5 V VISO Wide operating temperature range: −40°C to +105°C High common-mode transient immunity: 250 kV/µs Short-circuit, open-circuit, and floating input receiver fail-safe Supports 196 bus nodes (72 kΩ receiver input impedance) Full hot swap support (glitch free power-up/power-down) Safety and regulatory approvals (pending) CSA Component Acceptance Notice 5A, DIN V VDE V 0884-11, UL 1577, CQC11-471543-2012, IEC 61010-1 Complies with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E) 28-lead, fine pitch SOIC_W package (10.15 mm 10.05 mm) with >8.0 mm creepage and clearance

3 kV RMS Signal and Power Isolated RS-485 Transceiver with 15 kV IEC ESD Features: 3 kV rms isolated RS-485/RS-422 transceiver Low radiated emissions, integrated, isolated dc-to-dc converter Passes EN 55032 Class B with margin on a 2-layer PCB Cable invert smart feature Correct reversed cable connection on A, B, Y, and Z bus pins while maintaining full receiver fail-safe feature ESD protection on RS-485 A, B, Y and Z pins ≥±12 kV IEC61000-4-2 contact discharge ≥±15 kV IEC61000-4-2 air discharge High speed 25 Mbps data rate (ADM2565E/ADM2567E) Low speed 500 kbps data rate for EMI control (ADM2561E/ADM2563E) Flexible power supplies Input VCC supply of 3 V to 5.5 V Logic VIO supply of 1.7 V to 5.5 V VSEL pin to select VISO supply of 5 V (VCC > 4.5 V) or 3.3 V PROFIBUS compliant for 5 V VISO Wide operating temperature range: −40°C to +105°C High common-mode transient immunity: 250 kV/µs Short-circuit, open-circuit, and floating input receiver fail-safe Supports 196 bus nodes (72 kΩ receiver input impedance) Full hot swap support (glitch free power-up/power-down) Safety and regulatory approvals (pending) CSA Component Acceptance Notice 5A, DIN V VDE V 0884-11, UL 1577, CQC11-471543-2012, IEC 61010-1 Complies with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E) 28-lead, fine pitch SOIC_W package (10.15 mm 10.05 mm) with >8.0 mm creepage and clearance

5.7 kV RMS 500kbps Half Duplex Signal and Power Isolated RS-485 Transceiver with 15 kV IEC ESD Features: 5.7 kV rms isolated RS-485/RS-422 transceiver Low radiated emissions, integrated, isolated dc-to-dc converter Passes EN 55032 Class B with margin on a 2-layer PCB Cable invert smart feature Correct reversed cable connection on A, B, Y, and Z bus pins while maintaining full receiver fail-safe feature ESD protection on RS-485 A, B, Y, and Z pins 12 kV IEC61000-4-2 contact discharge 15 kV IEC61000-4-2 air discharge High speed 25 Mbps data rate (ADM2865E/ADM2867E) Low speed 500 kbps data rate for EMI control (ADM2861E/ADM2863E) Flexible power supplies Input VCC supply of 3 V to 5.5 V Logic VIO supply of 1.7 V to 5.5 V VSEL pin to select VISO supply of 5 V (VCC > 4.5 V) or 3.3 V PROFIBUS compliant for 5 V VISO Wide operating temperature range: −40°C to +105°C High common-mode transient immunity: 250 kV/μs Short-circuit, open-circuit, and floating input receiver fail-safe Supports 192 bus nodes (72 k receiver input impedance) Full hot swap support (glitch free power-up/power-down) Safety and regulatory approvals (pending) CSA Component Acceptance Notice 5A, DIN V VDE V 0884-11, UL 1577, CQC11-471543-2012, IEC 61010-1 Complies with ANSI/TIA/EIA-485-A-98 and ISO 8482:1987(E) 28-lead, fine pitch SOIC_W package (10.15 mm 10.05 mm) with >8.0 mm creepage and clearance