Digital Controller for Power Supply Applications with PMBus Interface Features: −40°C to +125°C operation with EEPROM data retention of 15 years at 125°C PMBus Revision 1.2 compliant 32-bit password protection with command masking 64 address selections (16 base addresses, expandable to 64) 6 PWM control signals, 625 ps resolution Duty cycle double update rate Digital control loop (PID + additional pole or zero configurability) Programmable loop filters (CCM, DCM, low/normal temperature) Frequency synchronization Soft start and soft stop functionality Average and peak constant current mode External PN junction temperature sensing 4 GPIOs (2 GPIOs configurable as active clamp snubber PWMs) Fast line voltage feedforward Adaptive dead time compensation for improved efficiency Extended black box data recorder for fault recording See datasheet for additional features

Isolated Synchronous Flyback Controller with Integrated iCoupler Features: Current mode controller for flyback topology ADP1071-1: programmable LLM or CCM for high VIN applications ADP1071-2: forced CCM operation Programmable slope compensation Integrated 5 kV isolation (wide body SOIC package) or 3.0 kV (LGA package) rated dielectric isolation voltage with Analog Devices, Inc., patented iCoupler technology Wide voltage supply range Primary VDD: up to 60 V (ADP1071-2 only) Secondary VDD2: up to 36 V Integrated 1 A primary side MOSFET driver Integrated 1 A secondary side MOSFET drivers for synchronous rectification Integrated error amplifier and <1% accurate reference voltage Programmable frequency range: 50 kHz to 600 kHz Duty cycle clamp limit 85% Programmable soft start and soft start from precharged load Protection features such as short circuit, output overvoltage, and overtemperature protection Power saving LLM using MODE pin (ADP1071-1only) Cycle by cycle input overcurrent protection Precision enable UVLO with hysteresis Frequency synchronization Safety and regulatory approvals (pending) UL recognition 5000 V rms for 1 minute per UL 1577 (for wide body SOIC package) 3000 V rms for 1 minute per UL 1577 (for LGA package) CSA Component Acceptance Notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 849 V peak (for wide body SOIC package) VIORM = 565 V peak (for LGA package) CQC certification per GB4943.1-2011 Available in 16-lead SOIC_W package and 24 terminal LGA package

Ultralow Noise, 150 mA CMOS Linear Regulator Features: Chinese data sheet available Ultralow noise: 9 μV rms, independent of VOUT No additional noise bypass capacitor required Stable with 1 μF ceramic input and output capacitors Maximum output current: 150 mA Input voltage range: 2.2 V to 5.5 V Low quiescent current IGND = 10 μA with zero load Low shutdown current: <1 μA Low dropout voltage: 105 mV at 150 mA load Initial output voltage accuracy: ±1% Up to 14 fixed output voltage options: 1.8 V to 3.3 V PSRR performance of 70 dB at 10 kHz Current limit and thermal overload protection Logic-controlled enable 5-lead TSOT package 4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP AEC-Q100 qualified for automotive applications

150 mA, Low Dropout, CMOS Linear Regulator Features: Maximum output current: 150 mA Input voltage range: 2.5 V to 5.5 V Light load efficient IGND = 35 μA with zero load IGND = 40 μA with 100 μA load Low shutdown current: <1 μA Low dropout voltage: 150 mV @ 150 mA load Initial accuracy: ±1% Accuracy over line, load, and temperature: ±2% Stable with small 1 μF ceramic output capacitor 16 fixed output voltage options: 0.75 V to 3.3 V (ADP1710) Adjustable output voltage option: 0.8 V to 5.0 V (ADP1710 Adjustable) 16 fixed output voltage options with reference bypass: 0.75 V to 3.3 V (ADP1711) High PSRR: 69 dB @ 1 kHz

300 mA, Low Dropout CMOS Linear Regulator Features: Maximum output current: 300 mA Input voltage range: 2.5 V to 5.5 V Light load efficient IGND = 75 μA with 100 μA load Low shutdown current: <1 μA Very low dropout voltage: 170 mV @ 300 mA load Initial accuracy: ±1% Accuracy over line, load, and temperature: ±2% 16 fixed output voltage options with tracking: 0.75 V to 3.3 V Low output noise: 40 μV rms High PSRR: 72 dB @ 1 kHz Stable with small 2.2 μF ceramic output capacitor See data sheet for additional features

1 A, Low VIN, Low Noise, CMOS Linear Regulator Features: 1 A maximum output current Low input voltage supply range VIN = 1.10 V to 1.98 V, no external bias supply required Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V Ultralow noise: 2 μV rms, 100 Hz to 100 kHz Noise spectral density 4 nV/√Hz at 10 kHz 3 nV/√Hz at 100 kHz Low dropout voltage: 30 mV typical at 1 A load Operating supply current: 4.5 mA typical at no load ±1.5% fixed output voltage accuracy over line, load, and temperature Excellent power supply rejection ratio (PSRR) performance 67 dB typical at 10 kHz at 1 A load 51 dB typical at 100 kHz at 1 A load Excellent load/line transient response Soft start to reduce inrush current Optimized for small 10 μF ceramic capacitors Current-limit and thermal overload protection Power-good indicator Precision enable 16-lead, 3 mm × 3 mm LFCSP package AEC-Q100 qualified for automotive applications

50 V, 130 kHz, 32.5 A, Robust, Over-The-Top Precision Op Amp Features: Ultrawide common-mode input range: −VS − 0.1 V to −VS + 70 V Wide power supply voltage range: +3 V to +50 V (to ±25 V for PSRR) Low power supply current: 32.5 μA (typical) Low input offset voltage: ±60 μV maximum Low input offset voltage drift: ±1 μV/°C maximum (B grade) Low input voltage noise 6 Hz typical 1/f noise corner 1000 nV p-p typical at 0.1 Hz to 10 Hz GBP: 130 kHz typical for fTEST = 250 Hz Slew rate: 0.1 V/μs typical at ΔVOUT = 4 V Low power supply current shutdown: 20 μA maximum Low input offset current: ±300 pA maximum Large signal voltage gain: 120 dB minimum for ΔVOUT = 3.5 V CMRR: 120 dB minimum at VCM = −0.1 V to +70 V PSRR: 123 dB minimum at VSY = +3 V to ±25 V Input overdrive tolerant with no phase reversal ±2 kV HBM and ±1.25 kV FICDM Wide temperature range: −55°C to +150°C (H grade) Shutdown feature available for single 6-lead TSOT and dual 10-lead LFCSP packages

50 V, 8 MHz, 1.5 mA per Channel, Robust, Over-The-Top, Precision Op Amps Features: Ultrawide common-mode range: −VS − 0.1 V to −VS + 70 V Wide power supply voltage range: (VSY): +3.15 V to +50 V (±25 V for PSRR) Low supply current: 1.5 mA per channel (typical) Low input offset voltage: ±40 μV maximum Low input offset voltage drift: ±0.4 μV/°C maximum Low voltage noise: 1/f noise corner: 6 Hz typical 150 nV p-p typical at 0.1 Hz to 10 Hz 7 nV/√Hz typical at 100 Hz (en) High speed GBP: 8 MHz typical Slew rate: 5.5 V/μs typical at ΔVOUT = 25 V Low power shutdown: 20 μA maximum Low input bias current: ±10 nA maximum Large signal voltage gain: 120 dB minimum CMRR: 118 dB, minimum PSRR: 123 dB, minimum Input overdrive tolerant with no phase reversal ±2 kV HBM and ±1.25 kV FICDM Wide temperature range: −55°C to +150°C (H grade)

OVP and EMI Protected, Precision, Low Noise and Bias Current Single Op Amp Features: Low offset voltage: 60 μV maximum at 25°C (8-lead and 14-lead SOIC) Low offset voltage drift: 1 μV/°C maximum (8-lead and 14-lead SOIC) Low input bias current: 1 nA maximum at 25°C Low voltage noise density: 8 nV/√Hz typical at 1 kHz Large signal voltage gain (AVO): 100 dB minimum over full supply voltage and operating temperature Input overvoltage protection to 32 V above and below the supply voltage rail Integrated EMI filter 70 dB typical rejection at 1000 MHz 90 dB typical rejection at 2400 MHz Rail-to-rail output swing Low supply current: 500 μA typical per amplifier Wide bandwidth Gain bandwidth product (AV = 100): 3.5 MHz typical Unity-gain crossover (AV = 1): 3.5 MHz typical −3 dB bandwidth (AV = 1): 6 MHz typical Dual-supply operation Specified at ±5 V to ±15 V, operates over ±2.5 V to ±18 V Unity-gain stable No phase reversal Long-term offset voltage drift (10,000 hours): 2 μV typical Temperature hysteresis: 2 μV typical

16-Bit, 15 MSPS, Module Data Acquisition Solution Features: Integrated fully differential ADC driver with signal scaling Wide input common range High common-mode rejection Single-ended to differential conversion 2.048 V input range with 4.096 V REFBUF Critical passive components 0.005% precision matched resistor array for FDA 9 mm × 9 mm, 0.8 mm pitch, 100-ball BGA package 4× footprint reduction versus discrete solution Low power, dynamic power scaling, power-down mode 143 mW typical at 15 MSPS Throughput: 15 MSPS, no pipeline delay INL: 0.4 LSB typical, 1 LSB maximum SINAD: 89 dB typical at 1 kHz THD: 115 dB at 1 kHz, 106 dB at 400 kHz Gain error: 0.005% FS typical Gain error drift: 1 ppm/C maximum On-board reference buffer with VCMO generation Serial LVDS interface Wide operating temperature range: 40C to +85C