Dual, 12-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP

10-/12-Bit Mixed Signal Front-End (MxFE) Processor for Broadband Communications Features: Dual 10-/12-Bit, 64 MSPS Sampling A/D Converter with Independent Reference, Input Buffers, Programmable Gain Amplifiers (PGA), Decimation Filters and a Digital Hilbert Block Dual 12-/14-bit, 128 MSPS D/A Converter with Digital Hilbert and Interpolation Filters, Digital I/Q or Real-Signal Up-Converters, By passable Digital Up-Converters A Versatile Mixed Signal Front-End Processor with Dual Receive and Dual Transmit Channels Internal Clock Distribution Block including a Phase-Locked Loop and Timing Generation circuitry Programmable Output Clocks, SPI Port, Programmable Sigma Delta Outputs, Auxiliary DAC outputs, Auxiliary ADC inputs

Broadband Modem Mixed-Signal Front End Features: Low cost, 3.3 V CMOS MxFE® for broadband modems 10-bit digital-to-analog converter (DAC) 2×/4× interpolation filter 250 MSPS DAC update rate 10-bit, 75 MSPS ADC Low noise RxPGA Dual channel muxed input 6 dB input overload attenuator −12 dB to +48 dB (without attenuator) Third-order programmable low-pass filter Flexible digital datapath interface Half-duplex and full-duplex operation Programmable delay Tx driver disable signal Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs 64-lead LFCSP

High Performance 8-Bit Display Interface Features: 8-bit analog-to-digital converters 140 MSPS maximum conversion rate Low PLL clock jitter at 140 MSPS Automatic gain matching Automated offset adjustment 2:1 input mux Power-down via dedicated pin or serial register 4:4:4, 4:2:2, and DDR output format modes Variable output drive strength Odd/even field detection External clock input Regenerated Hsync output

110 MSPS/140 MSPS Analog Interface for Flat Panel Displays Features: Automated clamping level adjustment 140 MSPS maximum conversion rate 300 MHz analog bandwidth 0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 110 MSPS 3.3 V power supply Full sync processing Sync detect for hot plugging Midscale clamping Power-down mode Low power: 500 mW typical 4:2:2 output format mode

High Speed, 5 V, 0.1 F CMOS RS-232 Driver/Receiver Features: 120 kB transmission rate Small (0.1 µF) charge pump capacitors Single 5 V power supply Meets TIA/EIA-232-E and V.28 specifications 2 drivers and 2 receivers On-board dc-to-dc converters ±9 V output swing with 5 V supply Low power BiCMOS: 2.5 mA ICC ±30 V receiver input levels

Equalisers Front Panel HDMI Buffer - TMDS Only

Operational Amplifiers - Op Amps VLTG-FDBK, G= 2 CLAMP AMP

Charge Pump, 7-Channel Smart LED Driver with I2C Interface Features: Charge pump with automatic gain selection of 1×, 1.5×, and 2× for maximum efficiency 7 independent, programmable LED drivers 7 drivers capable of 30 mA (typical) 1 driver also capable of 60 mA (typical) Programmable maximum current limit (128 levels) Standby mode for <1 μA current consumption 16 programmable fade in and fade out time 0.1 sec to 5.5 sec Choose from linear, square, or cubic rates Fading override I2C-compatible interface for all programming Dedicated reset pin and built-in power-on reset (POR) Short-circuit, overvoltage, and overtemperature protection Internal soft start to limit inrush currents Input-to-output isolation during faults or shutdown Operation down to VIN = 2.5 V with undervoltage lockout (UVLO) at VIN = 2.0 V Available in a small 20-ball, 2.15 mm × 2.36 mm × 0.6 mm WLCSP or a 20-lead, 4 mm × 4 mm × 0.75 mm LFCSP

3-V, RS-232 Serial Port Driver-Receiver Features: Green Idle power-saving mode Single 2.7 V to 3.6 V power supply Operates with 3 V logic 0.1 µF to 1 µF charge pump capacitors Low EMI Low power shutdown: 20 nA Full RS-232 compliance 460 kb/s data rate One receiver active in shutdown (ADM3307E/ADM3311E/ADM3312E/ADM3315E) Two receivers active in shutdown (ADM3310E) ESD >15 kV IEC 1000-4-2 on RS-232 I/Os ESD >15 kV IEC 1000-4-2 on CMOS and RS-232 I/Os (ADM3307E) Qualified for automotive applications