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|
Texas Instruments
TLV8542RUGR
|
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TL5001QDG4
|
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SN74AHC1G08DCKR
|
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NE5532DG4
|
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SN75155DE4
|
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F280041PZQR
|
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UCC28951PWR
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LM239ADG4
|
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OPA2335AIDG4
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| Price |
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| RoHS |
|
Y |
Compliant |
Compliant |
Compliant |
Compliant |
Y |
Compliant |
Compliant |
Compliant |
| Lead Status |
|
See ti.com |
No |
No |
No |
No |
Y |
See ti.com |
No |
No |
| Output current(Typ)(mA) |
|
15 |
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| Features |
|
Cost Optimized,EMI Hardened |
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|
FPU32,Configurable Logic Block,AEC Q100 |
Adjustable Switching Frequency,Current Limiting,Enable/Shutdown,Error Amplifier,Green Mode,Light Load Efficiency,Programmable Slope Compensation,Soft Start,Soft Switching,Synchronization Pin,Thermal Shutdown |
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| Output swing headroom (to positive supply)(Typ)(V) |
|
-0.012 |
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| Vos (offset voltage @ 25 C)(Max)(mV) |
|
3.1 |
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| Offset drift(Typ)(uV/C) |
|
0.8 |
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| Rating |
|
Catalog |
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Catalog |
Catalog |
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| Package Group |
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SOIC|8,X2QFN|8 |
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LQFP|100,LQFP|64,VQFN|56 |
TSSOP|24 |
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| Input common mode headroom (to positive supply)(Typ)(V) |
|
0.0005 |
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| Rail-to-rail |
|
In,Out |
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| GBW(Typ)(MHz) |
|
0.008 |
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| Iq per channel(Typ)(mA) |
|
0.0005 |
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| Vn at 1 kHz(Typ)(nV/rtHz) |
|
264 |
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| Architecture |
|
CMOS |
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| Slew rate(Typ)(V/us) |
|
0.0035 |
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| Package size |
|
mm2 |
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| Total supply voltage(Max)(+5V=5, +/-5V=10) |
|
3.6 |
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| Number of channels(#) |
|
2 |
|
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| CMRR(Typ)(dB) |
|
80 |
|
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| Input common mode headroom (to negative supply)(Typ)(V) |
|
0.00064 |
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| Iq per channel(Max)(mA) |
|
0.00064 |
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| Operating temperature range(C) |
|
-40 to 125 |
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|
-40 to 125 |
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| Total supply voltage(Min)(+5V=5, +/-5V=10) |
|
1.7 |
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| Output swing headroom (to negative supply)(Typ)(V) |
|
0.012 |
|
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| Approx. price(US$) |
|
0.15 | 1ku |
|
|
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|
4.85 | 1ku |
|
|
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| RAM(KB) |
|
|
|
|
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|
100 |
|
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| I2C |
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|
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|
1 |
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| Sigma-delta filter |
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|
4,3 |
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| Total processing (MIPS) |
|
|
|
|
|
|
100 |
|
|
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| UART(SCI) |
|
|
|
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|
2 |
|
|
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| Flash(KB) |
|
|
|
|
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|
128 |
|
|
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| High-resolution PWM (ch) |
|
|
|
|
|
|
16 |
|
|
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| USB |
|
|
|
|
|
|
0 |
|
|
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| Frequency(MHz) |
|
|
|
|
|
|
100 |
|
|
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| DMA(Ch) |
|
|
|
|
|
|
6 |
|
|
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| ADC (Ch) |
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|
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|
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|
21,14,12 |
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| ADC resolution |
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|
12-bit |
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| PWM(Ch) |
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|
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|
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|
16 |
|
|
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| CAN(#) |
|
|
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|
2 |
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| SPI |
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|
2 |
|
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| QEP |
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|
2,1 |
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| Topology |
|
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|
Phase-Shifted Full-Bridge |
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| Frequency(Max)(kHz) |
|
|
|
|
|
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|
1000 |
|
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| Operating Temperature Range(C) |
|
|
|
|
|
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|
-40 to 125 |
|
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| Frequency(Min)(kHz) |
|
|
|
|
|
|
|
50 |
|
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| Approx. Price (US$) |
|
|
|
|
|
|
|
3.38 | 1ku |
|
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| UVLO Thresholds On/Off(V) |
|
|
|
|
|
|
|
7.3/6.7 |
|
|
| Duty Cycle(Max)(%) |
|
|
|
|
|
|
|
97 |
|
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| Control Method |
|
|
|
|
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|
|
Current,Peak Current Mode,Voltage |
|
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| VCC(Max)(V) |
|
|
|
|
|
|
|
17 |
|
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| VCC(Min)(V) |
|
|
|
|
|
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|
8 |
|
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| Gate Drive(Typ)(A) |
|
|
|
|
|
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|
0.2 |
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|
