Ultra-Low-Noise, High-Accuracy 2.5V Voltage Reference Features: Maximum temperature coefficient (TCVOUT): 0.8 ppm/°C (D grade 0°C to 70°C) 1 ppm/°C (C grade 0°C to 70°C) 2 ppm/°C (B grade −40°C to +125°C) 4 ppm/°C (A grade 40°C to +125°C) Output noise (0.1 Hz to 10 Hz): 1 μV p-p at VOUT of 2.048 V typical Initial output voltage error: B, C, D grade: ±0.02% (maximum) Input voltage range: 3 V to 15 V Operating temperature: A grade and B grade: −40°C to +125°C C grade: 0°C to +70°C Output current: +10 mA source/−10 mA sink Low quiescent current: 950 μA (maximum) Low dropout voltage: 300 mV at 2 mA (VOUT ≥ 3 V) 8-lead SOIC package and LCC package AEC-Q100 qualified for automotive applications Long-term drift: 8 ppm typical at 4500 hours

Ultra-Low-Noise, High-Accuracy 4.096V Voltage Reference Features: Maximum temperature coefficient (TCVOUT): 0.8 ppm/°C (D grade 0°C to 70°C) 1 ppm/°C (C grade 0°C to 70°C) 2 ppm/°C (B grade −40°C to +125°C) 4 ppm/°C (A grade 40°C to +125°C) Output noise (0.1 Hz to 10 Hz): 1 μV p-p at VOUT of 2.048 V typical Initial output voltage error: B, C, D grade: ±0.02% (maximum) Input voltage range: 3 V to 15 V Operating temperature: A grade and B grade: −40°C to +125°C C grade: 0°C to +70°C Output current: +10 mA source/−10 mA sink Low quiescent current: 950 μA (maximum) Low dropout voltage: 300 mV at 2 mA (VOUT ≥ 3 V) 8-lead SOIC package and LCC package AEC-Q100 qualified for automotive applications Long-term drift: 8 ppm typical at 4500 hours

Ultra-Low-Noise, High-Accuracy 4.096V Voltage Reference Features: Maximum temperature coefficient (TCVOUT): 0.8 ppm/°C (D grade 0°C to 70°C) 1 ppm/°C (C grade 0°C to 70°C) 2 ppm/°C (B grade −40°C to +125°C) 4 ppm/°C (A grade 40°C to +125°C) Output noise (0.1 Hz to 10 Hz): 1 μV p-p at VOUT of 2.048 V typical Initial output voltage error: B, C, D grade: ±0.02% (maximum) Input voltage range: 3 V to 15 V Operating temperature: A grade and B grade: −40°C to +125°C C grade: 0°C to +70°C Output current: +10 mA source/−10 mA sink Low quiescent current: 950 μA (maximum) Low dropout voltage: 300 mV at 2 mA (VOUT ≥ 3 V) 8-lead SOIC package and LCC package AEC-Q100 qualified for automotive applications Long-term drift: 8 ppm typical at 4500 hours

Ultra-Low-Noise, High-Accuracy 5.0V Voltage Reference Features: Maximum temperature coefficient (TCVOUT): 0.8 ppm/°C (D grade 0°C to 70°C) 1 ppm/°C (C grade 0°C to 70°C) 2 ppm/°C (B grade −40°C to +125°C) 4 ppm/°C (A grade 40°C to +125°C) Output noise (0.1 Hz to 10 Hz): 1 μV p-p at VOUT of 2.048 V typical Initial output voltage error: B, C, D grade: ±0.02% (maximum) Input voltage range: 3 V to 15 V Operating temperature: A grade and B grade: −40°C to +125°C C grade: 0°C to +70°C Output current: +10 mA source/−10 mA sink Low quiescent current: 950 μA (maximum) Low dropout voltage: 300 mV at 2 mA (VOUT ≥ 3 V) 8-lead SOIC package and LCC package AEC-Q100 qualified for automotive applications Long-term drift: 8 ppm typical at 4500 hours

Integrated Dual RF Tx, Rx, and Observation Rx Features: Dual transmitters Dual receivers Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz

Integrated Dual RF Tx, Rx, and Observation Rx Features: Dual transmitters Dual receivers Dual input shared observation receiver Maximum receiver bandwidth: 200 MHz Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz

High-Performance 32-bit Floating-Point SHARC Processor for General Purpose Applications Features: 400MHz SIMD SHARC Core, capable of 2.4 GFLOPS peak performance 2Mbits SRAM; 6 Mbits customer-definable ROM High bandwidth, 32-bit external memory interface supporting glue-less interface to SDRAM, SRAM, and FLASH Digital Audio Interface (DAI) enabling user-definable access to system peripherals including 8 serial ports (SPORTs), S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and 4 precision clock generators. Digital Peripheral Interface (DPI) enabling user-definable access to system peripherals including 2 SPI-compatible ports, 2 UARTs, 3 full-featured timers, and a two-wire interface compliant to the I2C standard. 34 zero-overhead DMA channels 16 Pulse Width Modulation (PWM) channels 208-lead LQFP-EP and 256-ball SBGA packages Commercial and industrial temperature ranges Maximum core performance is reduced for LQFP package

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 1GHz SHARC+ DSP with 640KB L1, 1024KB Shared L2 SRAM, 120-lead LQFP_EP Features:SHARC+ Core infrastructure 800MHz (max) or 1GHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 1024KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases Advanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 24 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 4x I2C, 2x UARTs 6x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 2-ch 12bit Housekeeping ADCs 22 GPIO pins, 24 DAI pins Thermal SensorPackage 14mm x 14mm 120-lead LQFP_EAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications

Up to 800MHz SHARC+ DSP with 640KB L1, 512KB Shared L2 SRAM, 400-Ball CSP_BGA Features:SHARC+ Core infrastructure 600MHz (max) or 800MHz (max) Core clock frequency 640KB on-chip Level 1 (L1) SRAM memory (with parity) increases low latency performance 32-bit, 40-bit & 64-bit floating point support 32-bit fixed point Byte, short-word, word, long-word addressedMemory 512KB on-chip Level 2 (L2) SRAM with ECC protection - eliminates need for external memory in many use cases One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.35 V capable DDR3L devices) SDRAM devices16-bit DDR/DDR3L Memory Controller 1.35V support for DDR3LAdvanced Hardware Accelerators Enhanced FIR/IIR offload engines running at Core clock frequency for added processing power Security Crypto Engines with OTPPowerful DMA SystemInnovative Digital Audio Interface (DAI) includes: 8x Full SPORT interfaces w/TDM & I2S modes 2x S/PDIF Rx/Tx, 8 ASRC pairs 4x Precision Clock Generators 28 BuffersOther Peripheral Connectivity / Interfaces: 2x Quad SPI, 1x Octal SPI MLB 3-pin 6x I2C,3x UARTs 2x Link Ports 10x General Purpose Timer, 1x General Purpose Counter 2x Watchdog Timers 4-ch 12bit Housekeeping ADCs 40 GPIO pins, 28 DAI pins Thermal SensorPackage 17mm x 17mm (0.8mm pitch) 400-ball CSP_BGAAdditional Features Security and Protection Crypto hardware accelerators Fast secure boot with IP protection Enhanced FIR and IIR accelerators running up to 1 GHz AEC-Q100 qualified for automotive applications