The AD8494/AD8495/AD8496/AD8497 are precision instrumentation amplifiers with thermocouple cold junction compensators on an integrated circuit. They produce a high level (5 mV/°C) output directly from a thermocouple signal by combining an ice point reference with a precalibrated amplifier. They can be used as standalone thermometers or as switched output setpoint controllers using either a fixed or remote setpoint control.The AD8494/AD8495/AD8496/AD8497 can be powered from a single-ended supply (less than 3 V) and can measure temperatures below 0°C by offsetting the reference input. To minimize self-heating, an unloaded AD849x typically operates with a total supply current of 180 μA, but it is also capable of delivering in excess of ±5 mA to a load.The AD8494 and AD8496 are precalibrated by laser wafer trimming to match the characteristics of J type (iron-constantan) thermocouples; the AD8495 and AD8497 are laser trimmed to match the characteristics of K type (chromel-alumel) thermo-couples. See Table 1 on the data sheet for the optimized ambient temperature range of each part.The AD8494/AD8495/AD8496/AD8497 allow a wide variety of supply voltages. With a 5 V single supply, the 5 mV/°C output allows the devices to cover nearly 1000 degrees of a thermo-couple’s temperature range.The AD8494/AD8495/AD8496/AD8497 work with 3 V supplies, allowing them to interface directly to lower supply ADCs. They can also work with supplies as large as 36 V in industrial systems that require a wide common-mode input range.Product Highlights Complete, precision laser wafer trimmed thermocouple signal conditioning system in a single IC package. Flexible pinout provides for operation as a setpoint controller or as a standalone Celsius thermometer. Rugged inputs withstand 4 kV ESD and provide over-voltage protection (OVP) up to VS ± 25 V. Differential inputs reject common-mode noise on the thermocouple leads. Reference pin voltage can be offset to measure 0°C on single supplies. Available in a small, 8-lead MSOP that is fully RoHS compliant.Applications K type thermocouple temperature measurement Setpoint controller Celsius thermometer Universal cold junction compensator White goods (oven, stove top) temperature measurements Exhaust gas temperature sensing Catalytic converter temperature sensing div#landing_page_sec ul { padding:0 0 15px 10px; margin:0px; } div#landing_page_sec li { padding:3px 0 2px 20px; margin:0px; list-style:none; background:url(/static/imported-files/embedded_html/images/li_img.gif) no-repeat 7px 9px; display:block; color:#000000; font-family: Arial, Helvetica, sans-serif; }

The AD8494/AD8495/AD8496/AD8497 are precision instrumentation amplifiers with thermocouple cold junction compensators on an integrated circuit. They produce a high level (5 mV/°C) output directly from a thermocouple signal by combining an ice point reference with a precalibrated amplifier. They can be used as standalone thermometers or as switched output setpoint controllers using either a fixed or remote setpoint control.The AD8494/AD8495/AD8496/AD8497 can be powered from a single-ended supply (less than 3 V) and can measure temperatures below 0°C by offsetting the reference input. To minimize self-heating, an unloaded AD849x typically operates with a total supply current of 180 μA, but it is also capable of delivering in excess of ±5 mA to a load.The AD8494 and AD8496 are precalibrated by laser wafer trimming to match the characteristics of J type (iron-constantan) thermocouples; the AD8495 and AD8497 are laser trimmed to match the characteristics of K type (chromel-alumel) thermo-couples. See Table 1 on the data sheet for the optimized ambient temperature range of each part.The AD8494/AD8495/AD8496/AD8497 allow a wide variety of supply voltages. With a 5 V single supply, the 5 mV/°C output allows the devices to cover nearly 1000 degrees of a thermo-couple’s temperature range.The AD8494/AD8495/AD8496/AD8497 work with 3 V supplies, allowing them to interface directly to lower supply ADCs. They can also work with supplies as large as 36 V in industrial systems that require a wide common-mode input range.Product Highlights Complete, precision laser wafer trimmed thermocouple signal conditioning system in a single IC package. Flexible pinout provides for operation as a setpoint controller or as a standalone Celsius thermometer. Rugged inputs withstand 4 kV ESD and provide over-voltage protection (OVP) up to VS ± 25 V. Differential inputs reject common-mode noise on the thermocouple leads. Reference pin voltage can be offset to measure 0°C on single supplies. Available in a small, 8-lead MSOP that is fully RoHS compliant. Applications J type thermocouple temperature measurement Setpoint controller Celsius thermometer Universal cold junction compensator White goods (oven, stove top) temperature measurements Exhaust gas temperature sensing Catalytic converter temperature sensing div#landing_page_sec ul { padding:0 0 15px 10px; margin:0px; } div#landing_page_sec li { padding:3px 0 2px 20px; margin:0px; list-style:none; background:url(/static/imported-files/embedded_html/images/li_img.gif) no-repeat 7px 9px; display:block; color:#000000; font-family: Arial, Helvetica, sans-serif; }

The AD9146 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency.The AD9146 TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 3-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9146 comes in a 48-lead LFCSP.PRODUCT HIGHLIGHTS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Compact LVDS digital interface offers reduced width data bus.APPILICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point

The AD9265 is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9265 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 16-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate.Combined with power and cost savings over previously available ADCs, the AD9265 is suitable for applications in communications, instrumentation and medical imaging. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.The AD9265 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipmentPRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock duty cycle stabilizer, DCS, power-down, test modes, and voltage reference mode. Pin compatibility with the AD9255, allowing a simple migration from 16 bits down to 14 bits.

The AD9265 is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9265 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 16-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate.Combined with power and cost savings over previously available ADCs, the AD9265 is suitable for applications in communications, instrumentation and medical imaging. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.The AD9265 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONS Communications Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipmentPRODUCT HIGHLIGHTS On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock duty cycle stabilizer, DCS, power-down, test modes, and voltage reference mode. Pin compatibility with the AD9255, allowing a simple migration from 16 bits down to 14 bits.

The AD9266 is a monolithic, single-channel 1.8 V supply,16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digitalconverter (ADC). It features a high performance sample-and-holdcircuit and on-chip voltage reference.The product uses multistage differential pipeline architecturewith output error correction logic to provide 16-bit accuracy at80 MSPS data rates and to guarantee no missing codes over thefull operating temperature range.The ADC contains several features designed to maximizeflexibility and minimize system cost, such as programmableclock and data alignment and programmable digital test patterngeneration. The available digital test patterns include built-indeterministic and pseudorandom patterns, along with customuser-defined test patterns entered via the serial port interface (SPI).A differential clock input with a selectable internal 1-to-8 divideratio controls all internal conversion cycles. An optional duty cyclestabilizer (DCS) compensates for wide variations in the clock dutycycle while maintaining excellent overall ADC performance.The interleaved digital output data is presented in offset binary,gray code, or twos complement format. A DCO is provided toensure proper latch timing with receiving logic. Both 1.8 V and3.3 V CMOS levels are supported.The AD9266 is available in a 32-lead RoHS-compliant LFCSPand is specified over the industrial temperature range (−40°Cto +85°C).Product Highlights The AD9266 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D15_D14 to D1_D0) timing and offset adjustments, and voltage reference modes. The AD9266 is packaged in a 32-lead RoHS-compliant LFCSP that is pin compatible with the AD9609 10-bit ADC, the AD9629 12-bit ADC, and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 80 MSPS.Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imaging

The AD9269 is a monolithic, dual-channel, 1.8 V supply, 16-bit, 20/40/65/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 16-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The AD9269 incorporates an optional integrated dc correction and quadrature error correction block (QEC) that corrects for dc offset, gain, and phase mismatch between the two channels. This functional block can be very beneficial to complex signal processing applications such as direct conversion receivers.The ADC also contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is pro-vided for each ADC channel to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported, and output data can be multiplexed onto a single output bus.The AD9269 is available in a 64-lead RoHS-compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR

The AD9467 is a 16-bit, monolithic, IF sampling analog-to-digital converter (ADC). It is optimized for high performance over wide bandwidths and ease of use. The product operates at a 250 MSPS conversion rate and is designed for wireless receivers, instrumentation, and test equipment that require a high dynamic range.The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit. The internal power-down feature supported via the SPI and typically consumes less than 5 mW when disabled.Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns. The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range. Product HighlightsIF optimization capability used to improve SFDR.Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture.Packaged in a Pb-free, 72-lead LFCSP package.Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths.Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding), enabling the clock DCS. ApplicationsMulticarrier, multimode cellular receiversAntenna array positioningPower amplifier linearizationBroadband wirelessRadarInfrared imagingCommunications instrumentation

The AD9523 provides a low power, multi-output, clock distribution function with low jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to 4.0 GHz.The AD9523 is designed to support the clock requirements for long term evolution (LTE) and multicarrier GSM base station designs. It relies on an external VCXO to provide the reference jitter cleanup to achieve the restrictive low phase noise requirements necessary for acceptable data converter SNR performance.The input receivers, oscillator, and zero delay receiver provide both single-ended and differential operation. When connected to a recovered system reference clock and a VCXO, the device generates 14 low noise outputs with a range of 1 MHz to 1 GHz, and one dedicated buffered output from the input PLL (PLL1). The frequency and phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a jitter-free coarse timing adjustment in increments that are equal to the period of the signal coming out of the VCO.An in-package EEPROM can be programmed through the serial interface to store user-defined register settings for power-up and chip reset.APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction (G.710) High performance wireless transceivers ATE and high performance instrumentation

The AD9629 is a monolithic, single channel 1.8 V supply, 12-bit, 20 MSPS/40 MSPS/65MSPS/80 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference.The product uses multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 80 MSPS data rates and to guarantee no missing codes over the full operating temperature range.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).A differential clock input with optional 1, 2, or 4 divide ratios controls all internal conversion cycles.The digital output data is presented in offset binary, gray code, or twos complement format. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. Both 1.8 V and 3.3 V CMOS levels are supported.The AD9629 is available in a 32-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C).Applications Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA Smart antenna systems Battery-powered instruments Hand held scope meters Portable medical imaging Ultrasound Radar/LIDAR PET/SPECT imagingProduct Highlights1. The AD9629 operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.2. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use.3. A standard serial port interface (SPI) supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO and data output (D11 to D0) timing and offset adjustments, and voltage reference modes.4. The AD9629 is packaged in a 32-lead RoHS compliant LFCSP that is pin compatible with the AD9609 10-bit ADC and the AD9649 14-bit ADC, enabling a simple migration path between 10-bit and 14-bit converters sampling from 20 MSPS to 80 MSPS.