Low Input Bias Current, Wide BW JFET Precision Dual Op Amp Features: Low Noise 6 nV/√Hz Low Offset Voltage: 100 µV Max Low Input Bias Current 10 pA Max Fast Settling: 600 ns to 0.01% Low Distortion Unity Gain Stable No Phase Reversal Dual-Supply Operation: ±5 V to ±13 V

High Voltage, Latch-Up Proof, 8-Channel Differential Multiplexer Features: Latch-up proof 3.5 pF off source capacitance 33 pF off drain capacitance 0.35 pC typical charge injection ±0.02 nA on channel leakage Low on resistance: 155 typical ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation VSS to VDD analog signal range Human body model (HBM) ESD rating - 8 kV I/O port to supplies

Fault Protection, 6 RON, SPST Switch with 0.6 k Feedback Channel Features: Analog output protection and detection solution Overvoltage protection up to 60 V on S and SFB pins Power off protection up to 60 V on S and SFB pins Integrated 0.6 k secondary feedback channel Known output under all conditions User enabled, power-on condition pulls source to 0 V Known state without digital inputs present Latch-up immune Optimized resistance for measurement channel and feedback channel Low on resistance of 6 typical on signal channel Ultraflat, on resistance on signal channel 3 mm 2 mm LFCS VSS to VDD 2 V signal range Fully specified at ±15 V, ±20 V, +12 V, and +36 V ±5 V to ±22 V dual supply operation 8 V to 44 V single-supply operation

CMOS, 2.5 Low Voltage Differential 8 Channel Multiplexer Features: +1.8 V to +5.5 V single supply ±2.5 V dual supply 2.5 ON resistance 0.5 ON resistance flatness 100 pA leakage currents 40 ns switching times Differential 8-to-1 multiplexer 28-lead TSSOP package Low-power consumption TTL/CMOS-compatible inputs

Low Voltage, 300 MHz Quad 2:1 Mux Analog HDTV Audio/Video Switch Features: Bandwidth: 300 MHz Low Insertion Loss and on Resistance: 5 typical On Resistance Flatness: 0.68 Typical Single 3 V/5 V Supply Operation Low Quiescent Supply Current: 1 nA Typical TTL/CMOS Compatible Fast switching times: tON, 7 ns; tOFF, 5 ns ESD protection 2 kV human body model (HBM) 200 V machine model (MM) 1 kV field-induced charged device model (FICDM)

Wideband, 43 dB Isolation at 1 GHz, CMOS 1.65 V to 2.75 V, 2:1 Mux/SPDT Switches Features: Wideband switch: −3 dB at 4 GHz Absorptive/reflective switches High off isolation (43 dB at 1 GHz) Low insertion loss (0.8 dB at 1 GHz) Single 1.65 V to 2.75 V power supply CMOS/LVTTL control logic 8-lead MSOP and tiny 3 mm × 3 mm LFCSP Low power consumption (<1 µA)

Precision, Miniature MEMS IMU Features: Triaxial, digital gyroscope ±125°/sec, ±500°/sec, ±2000°/sec dynamic range models 2.3°/hr in-run bias stability (ADIS16507-1) 0.13°/√hr angular random walk, x-axis and y-axis, 1 σ (ADIS16507-1) ±0.25° axis to axis misalignment error Triaxial, digital accelerometer, ±392 m/sec2 dynamic range 125 μm/sec2 in-run bias stability, x-axis and y-axis, 1 σ Triaxial, delta angle and delta velocity outputs Factory calibrated sensitivity, bias, and axial alignment Calibration temperature range: −40°C to +85°C SPI compatible data communications Programmable operation and control Automatic and manual bias correction controls Data ready indicator for synchronous data acquisition External sync modes: direct, scaled, and output On demand self-test of inertial sensors On demand self-test of flash memory Single-supply operation (VDD): 3.0 V to 3.6 V 19,600 m/sec2 mechanical shock survivability Operating temperature range: −40°C to +105°C

MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC Features:Flexible reconfigurable common platform design 4 DACs and 2 ADCs (4D2A) and 2D2A options Supports single, dual, and quad band Datapaths and DSP blocks are fully bypassableDAC to ADC sample rate ratios of 1, 2, 3, and 4 On-chip PLL with multichip synchronization External RFCLK input option for off-chip PLL Maximum DAC sample rate up to 12 GSPS Maximum data rate up to 12 GSPS using JESD204C Useable analog bandwidth to 8 GHz Maximum ADC sample rate up to 6 GSPS Maximum data rate up to 6 GSPS using JESD204C Useable analog bandwidth to 8 GHz ADC ac performance at 6 GSPS, input at 2.7 GHz, 1 dBFS Full-scale input voltage: 1.475 V p-p Noise density: 147.5 dBFS/Hz Noise figure: 25.3 dB HD2: 72 dBFS HD3: 68 dBFS Worst other (excluding HD2 and HD3): 78 dBFS DAC ac performance at 12 GSPS, output at 2.6 GHz Full-scale output current range: 6.43 mA to 37.75 mA Two-tone IMD3 (6 dBFS per tone): 72 dBc NSD, single-tone: 160 dBc/Hz SFDR, single-tone: 75 dBc Versatile digital features Selectable interpolation and decimation filters Configurable DDC and DUC 8 fine complex DUCs and 4 coarse complex DUCs 8 fine complex DDCs and 4 coarse complex DDCs 48-bit NCO per DUC or DDC Option to bypass fine and coarse DUC/DDC Programmable 192-tap PFIR filter for receive equalization Supports 4 different profile settings loaded via GPIO Programable delay per data path Receive AGC support Fast detect with low latency for fast AGC control Signal monitor for slow AGC control Dedicated AGC support pins Transmit DPD support Fine DUC channel gain control and delay adjust Coarse DDC delay adjust for DPD observation path Auxiliary features Fast frequency hopping Direct digital synthesis (DDS) Low latency loopback modes (receive datapath data can be routed to the transmit datapaths) ADC clock driver with selectable divide ratios Power amplifier downstream protection circuitry On-chip temperature monitoring unit Flexible GPIO pins TDD power savings option SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps 8 lanes JESD204B/C transmitter (JT×) and 8 lanes JESD204B/C receiver (JR×) JESD204B compliance with the maximum 15.5 Gbps JESD204C compliance with the maximum 24.75 Gbps Supports real or complex digital data (8-, 12-, 16-, or 24-bit) 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

OVP and EMI Protected, Precision, Low Noise and Bias Current Single Op Amp Features: Low offset voltage: 60 μV maximum at 25°C (8-lead and 14-lead SOIC) Low offset voltage drift: 1 μV/°C maximum (8-lead and 14-lead SOIC) Low input bias current: 1 nA maximum at 25°C Low voltage noise density: 8 nV/√Hz typical at 1 kHz Large signal voltage gain (AVO): 100 dB minimum over full supply voltage and operating temperature Input overvoltage protection to 32 V above and below the supply voltage rail Integrated EMI filter 70 dB typical rejection at 1000 MHz 90 dB typical rejection at 2400 MHz Rail-to-rail output swing Low supply current: 500 μA typical per amplifier Wide bandwidth Gain bandwidth product (AV = 100): 3.5 MHz typical Unity-gain crossover (AV = 1): 3.5 MHz typical −3 dB bandwidth (AV = 1): 6 MHz typical Dual-supply operation Specified at ±5 V to ±15 V, operates over ±2.5 V to ±18 V Unity-gain stable No phase reversal Long-term offset voltage drift (10,000 hours): 2 μV typical Temperature hysteresis: 2 μV typical

Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator Features: Fully specified rail-to-rail at VCC = 2.5 V to 5.5 V Input common-mode voltage from −0.2 V to VCC + 0.2 V Low glitch TTL-/CMOS-compatible output stage 40 ns propagation delay Low power 1 mW at 2.5 V Shutdown pin Programmable hysteresis Power supply rejection > 60 dB −40°C to +125°C operation