Dual, 12-Bit, 1 GSPS, Digital-to-Analog Converter Features: Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×, 4×, and 8× interpolator/coarse complex modulator allows carrier placement anywhere in DAC bandwidth Auxiliary DACs allow control of external VGA and offset control Multiple chip synchronization interface High performance, low noise PLL clock multiplier Digital inverse sinc filter 100-lead, exposed paddle TQFP

10-/12-Bit Mixed Signal Front-End (MxFE) Processor for Broadband Communications Features: Dual 10-/12-Bit, 64 MSPS Sampling A/D Converter with Independent Reference, Input Buffers, Programmable Gain Amplifiers (PGA), Decimation Filters and a Digital Hilbert Block Dual 12-/14-bit, 128 MSPS D/A Converter with Digital Hilbert and Interpolation Filters, Digital I/Q or Real-Signal Up-Converters, By passable Digital Up-Converters A Versatile Mixed Signal Front-End Processor with Dual Receive and Dual Transmit Channels Internal Clock Distribution Block including a Phase-Locked Loop and Timing Generation circuitry Programmable Output Clocks, SPI Port, Programmable Sigma Delta Outputs, Auxiliary DAC outputs, Auxiliary ADC inputs

Broadband Modem Mixed-Signal Front End Features: Low cost, 3.3 V CMOS MxFE® for broadband modems 10-bit digital-to-analog converter (DAC) 2×/4× interpolation filter 250 MSPS DAC update rate 10-bit, 75 MSPS ADC Low noise RxPGA Dual channel muxed input 6 dB input overload attenuator −12 dB to +48 dB (without attenuator) Third-order programmable low-pass filter Flexible digital datapath interface Half-duplex and full-duplex operation Programmable delay Tx driver disable signal Various power-down/reduction modes Internal clock multiplier (PLL) 2 auxiliary programmable clock outputs 64-lead LFCSP

60 Ohm, Quad SPST Switch Features: 44 V Supply Maximum Rating ±15 V Analog Signal Range Low RON (60Ω) Low Leakage (0.5nA) Break-Before-Make Switching Action Extended Plastic Temperature Range (-40ºC to +85ºC) Low Power Dissipation (33 mW) TTL/CMOS Compatible Superior Second Source for DG201A/HI201 16-Lead DIP/SOIC PackagesADG201A-EP supports defense and aerospace applications (AQEC standard) Download ADG201A-EP data sheet (pdf) Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly and test site One fabrication site Enhanced product change notification Qualification data available on request V62/12638 DSCC Drawing Number

Precision Wide-range (3 nA - 3 mA) High-Side Current Mirror Features: Accurately mirrors input current (1:1 ratio) over 6 decades - enables monitoring at low signal levels  Linearity 1% from 3 nA to 3 mA Stable mirror input voltage Voltage held 1 V below supply using internal reference or may be set externally providing greater flexibility in design Adjustable input current limit provides protection to the connected photodiode 2.7 V to 8 V single-supply operation Miniature 8-lead chip scale package (LFCSP 2 mm × 3 mm) saves valuable board space

10 MHz TO 10 GHz 67 dB TruPwr Detector Features: Accurate rms-to-dc conversion from 10 MHz to 10 GHz Single-ended ±1 dB dynamic range: 67 dB at 2.14 GHz    No balun or external input matching required Response independent of waveform types, such as GSM/CDMA/W-CDMA/TD-SCDMA/WiMAX/LTE Logarithmic slope: 55 mV/dB Temperature stability: <±1 dB from −40°C to +125°C Operating temperature: −55°C to +125°C Supply voltage: 4.75 V to 5.25 V Sleep current: 250 µA Pin-compatible with ADL5902 and AD8363

Ultrafast 3.3 V Single-Supply Comparator w/Reduced Swing PECL (RSPECL) Output Drivers Features: 3.3 V/5.2 V single-supply operation 150 ps propagation delay 15 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 80 ps minimum pulse width 35 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) On-chip terminations at both input pins Robust inputs with no output phase reversal Resistor-programmable hysteresis Differential latch control Extended industrial −40°C to +125°C temperature range

Ultrafast SiGe Voltage Comparator (Featuring Reduced Swing NECL Output Drivers) Features: 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) −2 V to +3 V input range with +5 V/−5 V supplies On-chip terminations at both input pins Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB

Single, Integer-N 550 MHz PLL Features: ADF4116: 550 MHz ADF4117: 1.2 GHz ADF4118: 3.0 GHz 2.7 V to 5.5 V power supply Separate VP allows extended tuning voltage in 3 V systems Y Grade: −40°C to +125°C Dual-modulus prescaler ADF4116: 8/9 ADF4117/ADF4118: 32/33 3-wire serial interface Digital lock detect Power-down mode Fastlock mode

High Performance 8-Bit Display Interface Features: 8-bit analog-to-digital converters 140 MSPS maximum conversion rate Low PLL clock jitter at 140 MSPS Automatic gain matching Automated offset adjustment 2:1 input mux Power-down via dedicated pin or serial register 4:4:4, 4:2:2, and DDR output format modes Variable output drive strength Odd/even field detection External clock input Regenerated Hsync output