The HMC311SC70(E) is a GaAs InGaP Heterojunction Bipolar Transistor (HBT) Gain Block MMIC SMT DC to 8 GHz amplifier. Packaged in an industry standard SC70, the amplifier can be used as either a cascadable 50 Ohm gain stage or to drive the LO port of HMC mixers with up to +15 dBm output power. The HMC311SC70(E) offers 15 dB of gain and an output IP3 of +30 dBm while requiring only 54 mA from a +5V supply. The Darlington topology results in reduced sensitivity to normal process variations, and yields excellent gain stability over temperature while requiring a minimal number of external bias components.Applications Cellular / PCS / 3G WiBro / WiMAX / 4G Fixed Wireless & WLAN CATV, Cable Modem & DBS Microwave Radio & Test Equipment

The HMC1034LP6GE is a low-noise, wide-band clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 125MHz and 3GHz range. The HMC1034LP6GE features low noise Phase Detector (PD) and Delta-Sigma modulator, capable of operating at up to 100MHz, permit wider loop-bandwidths with excellent spectral performance.The HMC1034LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-165dBc/Hz) makes the HMC1034LP6GE an ideal source for a variety of applications–such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SERDES) circuits, FPGAs and processors. The HMC1034LP6GE can also be used as an LO for 10G/40G/100G optical modules and transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency translation.The differential output of the HMC1034LP6GE includes a 2-bit output amplitude control which may be set via the SPI serial programming interface, and an output Mute function. The Delta-Sigma Modulator of the HMC1034LP6GE features Hittite’s Exact Frequency Mode, which enables users to generate output frequencies with close to 0 Hz frequency error.APPLICATIONS 10G/40G/100G Optical Modules, Transponders, Line Cards OTN and SONET/SDH Applications 1G/10G Ethernet Line Cards High Frequency Processor Clocks Low Jitter SAW Oscillator Replacement  Fiber Channel Interface Clocks Cellular/4G Infrastructure DDS Replacement 10G Optical Modules, Transponders, Line Cards

The HMC1035LP6GE is a low-noise, wide-band 3.3 V clock generator IC with a fractional-N Phase Locked Loop (PLL) that features an integrated Voltage Controlled Oscillator (VCO). The device provides differential clock outputs between 25 MHz and 2500 MHz range. The HMC1035LP6GE features a low noise Phase Detector (PD) and Delta-Sigma modulator, capable of operating at up to 100 MHz which permits wider loop-bandwidths and excellent spurious performance.The HMC1035LP6GE features industry leading phase noise and jitter performance, across the operating range, that enable it to improve link level jitter performance, Bit-Error-Rates (BER) and eye diagram metrics. The superior noise floor (<-162 dBc/Hz) makes the HMC1035LP6GE an ideal source for a variety of applications–such as clock references for high speed data converters, physical layer devices (PHY), serializer/deserializer (SER DES) circuits, FPGAs and processors. The HMC1035LP6GE can also be used as an LO for 10G/40G/100G optical modules and transponders, as well as primary reference clock for 10G/40G/100G line cards, and for jitter attenuation and frequency translation.The differential output of the HMC1035LP6GE can be set to either External Termination, which could be used for LVPECL operation, or Internal Termination for operation in an LVDS compatible mode or LVPECL. Additionally, an ouput swing adjustment makes the device flexible and compatible with a wide variety of signal level requirements. The output can be internally terminated to reduce component count and cost or could be terminated externally using standard LVPECL termination methods. An Output Mute function allows the user to shut off the outputs, such as may be required for board testing or debugging. The LVPECL/LVDS, amplitude select and Output Mute function are all programmed SPI serial programming.The HMC1035LP6GE is designed to select between a Power Priority or a Performance Priority mode. The Power Priority setting reduces the current consumption of the part, whereas the Performance Priority setting improves the Jitter and Phase Noise performance.The 24 bit Delta-Sigma Modulator further enhances Hittite’s Exact Frequency Mode, which enables users to generate output frequencies with 0 Hz frequency error in many applications.APPLICATIONS 10G/40G/100G Optical Modules, Transponders, Line Cards OTN and SONET /SDH Applications Data Converters, Sample Clock Generation Cellular/4G Infrastructure High Frequency Processor/FPGA Clocks Any Frequency Clock Rate Generation Low Jitter SAW Oscillator Replacement DDS Replacement Frequency Translation Frequency Margining

The AD5668 device is a low power, octal, 16-bit, buffered voltage-output DAC. All devicesoperate from a single 2.7 V to 5.5 V supply and are guaranteedmonotonic by design. The AD5668 and AD5628 are available inboth a 4 mm × 4 mm LFCSP and a 16-lead TSSOP, while theAD5648 is available in both a 14-lead and 16-lead TSSOP.The AD5628/AD5648/AD5668 have an on-chip reference withan internal gain of 2. The AD5628-1/AD5648-1/AD5668-1 havea 1.25 V 5 ppm/°C reference, giving a full-scale output rangeof 2.5 V; the AD5628-2/AD5648-2/AD5668-2 and AD5668-3 havea 2.5 V 5 ppm/°C reference, giving a full-scale output range of5 V. The on-board reference is off at power-up, allowing the useof an external reference. The internal reference is enabled via asoftware write.The part incorporates a power-on reset circuit that ensures that theDAC output powers up to 0 V (AD5628-1/AD5648-1/AD5668-1,AD5628-2/AD5648-2/AD5668-2) or midscale (AD5668-3) andremains powered up at this level until a valid write takes place.The part contains a power-down feature that reduces the currentconsumption of the device to 400 nA at 5 V and provides software-selectable output loads while in power-down mode for any or allDAC channels. The outputs of all DACs can be updated simultaneouslyusing the LDAC function, with the added functionalityof user-selectable DAC channels to simultaneously update. Thereis also an asynchronous CLR that updates all DACs to a userprogrammablecode—zero scale, midscale, or full scale.The AD5628/AD5648/AD5668 utilize a versatile 3-wire serialinterface that operates at clock rates of up to 50 MHz and iscompatible with standard SPI®, QSPI™, MICROWIRE™, andDSP interface standards. The on-chip precision output amplifierenables rail-to-rail output swing.Product Highlights Octal, 12-/14-/16-bit DAC. On-chip 1.25 V/2.5 V, 5 ppm/°C reference. Available in 14-lead/16-lead TSSOP, 16-lead LFCSP, and 16-ball WLCSP. Power-on reset to 0 V or midscale. Power-down capability. When powered down, the DAC typically consumes 200 nA at 3 V and 400 nA at 5 V. Applications Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

The AD600/AD602 dual channel, low noise, variable gain amplifiers are optimized for use in ultrasound imaging systems, but are applicable to any application requiring precise gain, low noise and distortion, and wide bandwidth. Each independent channel provides a gain of 0 dB to +40 dB in the AD600 and -10 dB to +30 dB in the AD602. The lower gain of the AD602 results in an improved signal-to-noise ratio (SNR) at the output. However, both products have the same 1.4 nV/√Hz input noise spectral density. The decibel gain is directly proportional to the control voltage, accurately calibrated, and supply and temperature-stable.To achieve the difficult performance objectives, a proprietary circuit form, the X-AMP®, was developed. Each channel of the X-AMP comprises a variable attenuator of 0 dB to -42.14 dB followed by a high speed fixed gain amplifier. In this way, the amplifier never has to cope with large inputs, and can benefit from the use of negative feedback to precisely define the gain and dynamics. The attenuator is realized as a 7-stage R-2R ladder network having an input resistance of 100 W, laser trimmed to ±2%. The attenuation between tap points is 6.02 dB; the gain-control circuit provides continuous interpolation between these taps. The resulting control function is linear in dB.The gain-control interfaces are fully differential, providing an input resistance of ~15 M W and a scale factor of 32 dB/V (that is, 31.25 mV/dB) defined by an internal voltage reference. The response time of this interface is less than 1 µs. Each channel also has an independent gating facility that optionally blocks signal transmission and sets the dc output level to within a few millivolts of the output ground. The gating control input is TTL- and CMOS-compatible.The maximum gain of the AD600 is 41.07 dB, and the maximum gain of the AD602 is 31.07 dB; the -3 dB bandwidth of both models is nominally 35 MHz, essentially independent of the gain. The SNR for a 1 V rms output and a 1 MHz noise bandwidth is typically 76 dB for the AD600 and 86 dB for the AD602. The amplitude response is flat within ±0.5 dB from 100 kHz to 10 MHz; over this frequency range, the group delay varies by less than ±2 ns at all gain settings.Each amplifier channel can drive 100 W load impedances with low distortion. For example, the peak specified output is ±2.5 V minimum into a 500 W load, or ±1 V into a 100 W load. For a 200 W load in shunt with 5 pF, the total harmonic distortion for a ±1 V sinusoidal output at 10 MHz is typically -60 dBc.The AD600J/AD602J are specified for operation from 0°C to 70°C and are available in 16-lead PDIP (N) and 16-lead SOIC packages. The AD600A/AD602A are specified for operation from -40°C to +85°C and are available in 16-lead CERDIP (Q) and 16-lead SOIC packages. The AD600S/AD602S are specified for operation from -55°C to +125°C, are available in a 16-lead CERDIP (Q) package, and are MIL-STD-883 compliant. The AD600S/AD602S are also available under DESC SMD 5962-94572.AD600 - Gain Range: 0 dB to 40 dBAD602 - Gain Range: -10 dB to + 30 dB

The AD600/AD602 dual channel, low noise, variable gain amplifiers are optimized for use in ultrasound imaging systems, but are applicable to any application requiring precise gain, low noise and distortion, and wide bandwidth. Each independent channel provides a gain of 0 dB to +40 dB in the AD600 and –10 dB to +30 dB in the AD602. The lower gain of the AD602 results in an improved signal-to-noise ratio (SNR) at the output. However, both products have the same 1.4 nV/√Hz input noise spectral density. The decibel gain is directly proportional to the control voltage, accurately calibrated, and supply and temperature-stable.To achieve the difficult performance objectives, a proprietary circuit form, the X-AMP®, was developed. Each channel of the X-AMP comprises a variable attenuator of 0 dB to –42.14 dB followed by a high speed fixed gain amplifier. In this way, the amplifier never has to cope with large inputs, and can benefit from the use of negative feedback to precisely define the gain and dynamics. The attenuator is realized as a 7-stage R-2R ladder network having an input resistance of 100 W, laser trimmed to ±2%. The attenuation between tap points is 6.02 dB; the gain-control circuit provides continuous interpolation between these taps. The resulting control function is linear in dB.The gain-control interfaces are fully differential, providing an input resistance of ~15 M W and a scale factor of 32 dB/V (that is, 31.25 mV/dB) defined by an internal voltage reference. The response time of this interface is less than 1 µs. Each channel also has an independent gating facility that optionally blocks signal transmission and sets the dc output level to within a few millivolts of the output ground. The gating control input is TTL- and CMOS-compatible.The maximum gain of the AD600 is 41.07 dB, and the maximum gain of the AD602 is 31.07 dB; the –3 dB bandwidth of both models is nominally 35 MHz, essentially independent of the gain. The SNR for a 1 V rms output and a 1 MHz noise bandwidth is typically 76 dB for the AD600 and 86 dB for the AD602. The amplitude response is flat within ±0.5 dB from 100 kHz to 10 MHz; over this frequency range, the group delay varies by less than ±2 ns at all gain settings.Each amplifier channel can drive 100 W load impedances with low distortion. For example, the peak specified output is ±2.5 V minimum into a 500 W load, or ±1 V into a 100 W load. For a 200 W load in shunt with 5 pF, the total harmonic distortion for a ±1 V sinusoidal output at 10 MHz is typically -60 dBc.The AD600J/AD602J are specified for operation from 0°C to 70°C and are available in 16-lead PDIP (N) and 16-lead SOIC packages. The AD600A/AD602A are specified for operation from –40°C to +85°C and are available in 16-lead CERDIP (Q) and 16-lead SOIC packages. The AD600S/AD602S are specified for operation from –55°C to +125°C, are available in a 16-lead CERDIP (Q) package, and are MIL-STD-883 compliant. The AD600S/AD602S are also available under DESC SMD 5962-94572.AD600 - Gain Range: 0 dB to 40 dBAD602 - Gain Range: –10 dB to + 30 dB

The AD606 is a complete, monolithic logarithmic amplifier using a 9-stage 'successive-detection' technique. It provides both logarithmic and limited outputs. The logarithmic output is from a three-pole post-demodulation low-pass filter and provides a loadable output voltage of +0.1 V dc to +4 V dc. The logarithmic scaling is such that the output is +0.5 V for a sinusoidal input of -75 dBm and +3.5 V at an input of +5 dBm; over this range the logarithmic linearity is typically within ±0.4 dB. All scaling parameters are proportional to the supply voltage.The AD606 can operate above and below these limits, with reduced linearity, to provide as much as 90 dB of conversion range. A second low-pass filter automatically nulls the input offset of the first stage down to the submicrovolt level. Adding external capacitors to both filters allows operation at input frequencies as low as a few hertz.The AD606's limiter output provides a hard-limited signal output as a differential current of ±1.2 mA from open-collector outputs. In a typical application, both of these outputs are loaded by 200 Ω resistors to provide a voltage gain of more than 90 dB from the input. Transition times are 1.5 ns, and the phase is stable to within ±3° at 10.7 MHz for signals from -75 dBm to +5 dBm.The logarithmic amplifier operates from a single +5 V supply and typically consumes 65 mW. It is enabled by a CMOS logic level voltage input, with a response time of <5 µs. When disabled, the standby power is reduced to <1 mW within 5 µs.The AD606J is specified for the commercial temperaturerange of 0°C to +70°C and is available in 16-pin plastic DIPs or SOICs. Consult the factory for other packages and temperature ranges. An evaluation board is available for this product and may be ordered using the following product number: AD606-EB.APPLICATIONS Ultrasound and Sonar Processing Phase-Stable Limiting Amplifier to 100 MHz Received Signal Strength Indicator (RSSI) Wide Range Signal and Power Measurement

The AD627 is an integrated, micropower instrumentation amplifier that delivers rail-to-rail output swing on single and dual (+2.2 V to ±18 V) supplies. The AD627 provides excellent ac and dc specifications while operating at only 85 μA maximum.The AD627 offers superior flexibility by allowing the user to set the gain of the device with a single external resistor while con-forming to the 8-lead industry-standard pinout configuration. With no external resistor, the AD627 is configured for a gain of 5. With an external resistor, it can be set to a gain of up to 1000.A wide supply voltage range (+2.2 V to ±18 V) and micropower current consumption make the AD627 a perfect fit for a wide range of applications. Single-supply operation, low power consumption, and rail-to-rail output swing make the AD627 ideal for battery-powered applications. Its rail-to-rail output stage maximizes dynamic range when operating from low supply voltages. Dual-supply operation (±15 V) and low power consumption make the AD627 ideal for industrial applications, including 4 to 20 mA loop-powered systems.The AD627 does not compromise performance, unlike other micropower instrumentation amplifiers. Low voltage offset, offset drift, gain error, and gain drift minimize errors in the system. The AD627 also minimizes errors over frequency by providing excellent CMRR over frequency. Because the CMRR remains high up to 200 Hz, line noise and line harmonics are rejected.The AD627 provides superior performance, uses less circuit board area, and costs less than micropower discrete designs.Applications4 mA to 20 mA loop-powered applicationsLow power medical instrumentation—ECG, EEGTransducer interfacingThermocouple amplifiersIndustrial process controlsLow power data acquisitionPortable battery-powered instruments

The AD640 is a complete monolithic logarithmic amplifier. A singleAD640 provides up to 50 dB of dynamic range for frequenciesfrom dc to 120 MHz. Two AD640s in cascade can provide up to95 dB of dynamic range at reduced bandwidth. The AD640 uses asuccessive detection scheme to provide an output current proportionalto the logarithm of the input voltage. It is laser calibrated toclose tolerances and maintains high accuracy over the full militarytemperature range using supply voltages from ±4.5 V to ±7.5 V.The AD640 comprises five cascaded dc-coupled amplifier/limiterstages, each having a small signal voltage gain of 10 dB and a –3 dBbandwidth of 350 MHz. Each stage has an associated full-wavedetector, whose output current depends on the absolute value of itsinput voltage. The five outputs are summed to provide the videooutput (when low-pass filtered) scaled at 1 mA per decade (50 µAper dB). On chip resistors can be used to convert this output currentto a voltage with several convenient slope options. A balancedsignal output at +50 dB (referred to input) is provided to operateAD640s in cascade.The logarithmic response is absolutely calibrated to within ±1 dBfor dc or square wave inputs from ±0.75 mV to ±200 mV, withan intercept (logarithmic offset) at 1 mV dc. An integral X10attenuator provides an alternative input range of ±7.5 mV to±2 V dc. Scaling is also guaranteed for sinusoidal inputs.The AD640B is specified for the industrial temperature range of–40°C to +85°C and the AD640T, available processed to MILSTD-883B,for the military range of –55°C to +125°C. Both areavailable in 20-lead side-brazed ceramic DIPs or leadless chipcarriers (LCC). The AD640J is specified for the commercialtemperature range of 0°C to +70°C, and is available in both20-lead plastic DIP (N) and PLCC (P) packages.This device is now available to Standard Military Drawing(DESC) number 5962-9095501MRA and 5962-9095501M2A.Product Highlights Absolute calibration of a wideband logarithmic amplifier is unique. The AD640 is a high accuracy measurement device, not simply a logarithmic building block. Advanced design results in unprecedented stability over the full military temperature range. The fully differential signal path greatly reduces the risk of instability due to inadequate power supply decoupling and shared ground connections, a serious problem with commonly used unbalanced designs. Differential interfaces also ensure that the appropriate ground connection can be chosen for each signal port. They further increase versatility and simplify applications. The signal input impedance is ~500 kΩ in shunt with ~2 pF. The dc-coupled signal path eliminates the need for numerous interstage coupling capacitors and simplifies logarithmic conversion of subsonic signals. The low input offset voltage of 50 µV (200 µV max) ensures good accuracy for low level dc inputs. Thermal recovery “tails,” which can obscure the response when a small signal immediately follows a high level input, have been minimized by special attention to design details. The noise spectral density of 2 nV/√Hz results in a noise floor of ~23 µV rms (–80 dBm) at a bandwidth of 100 MHz. The dynamic range using cascaded AD640s can be extended to 95 dB by the inclusion of a simple filter between the two devices.Applications Radar, sonar, ultrasonic and audio systems Precision instrumentation from DC to 120 MHz Power measurement with absolute calibration Wide range high accuracy signal compression Alternative to discrete and hybrid IF strips Replaces several discrete log amp ICs

The AD652 Synchronous Voltage-to-Frequency Converter (SVFC) is a powerful building block for precision analog-to-digital conversion, offering typical nonlinearity of 0.002% (0.005% maximum) at a 100 kHz output frequency. The inherent monotonicity of the transfer function and wide range of clock frequencies allows the conversion time and resolution to be optimized for specific applications.The AD652 uses a variation of the popular charge-balancing technique to perform the conversion function. The AD652 uses an external clock to define the full-scale output frequency, rather than relying on the stability of an external capacitor. The result is a more stable, more linear transfer function, with significant application benefits in both single and multichannel systems.Gain drift is minimized using a precision low drift reference and low TC on-chip thin-film scaling resistors. Furthermore, the initial gain error is reduced to less than 0.5% by the use of laser-wafer-trimming.The analog and digital sections of the AD652 have been designed to allow operation from a single-ended power source, simplifying its use with isolated power supplies.The AD652 is available in five performance grades. The 20-pin PLCC packaged JP and KP grades are specified for operation over the 0°C to +70°C commercial temperature range. The 16-pin CERDIP-packaged AQ and BQ grades are specified for operation over the -40°C to +85°C industrial temperature range, and the AD652SQ is available for operation over the full -55°C to +125°C extended temperature range.