10 GHz to 40 GHz, 1:4 Channel, 4 Frequency Multiplier/Filter Features: 4 input frequency multiplier with programmable harmonic filter Quad Differential Output PAs with independent Enable Control Input Frequency Range: 2.5 GHz to 10 GHz Output Frequency Range: 10 GHz to 40 GHz Input power: 20 dBm (50 ) Output power: 5 dBm differential (100 ) Harmonic rejection: 20 dBc to 40 dBc at all frequencies 3-Wire or 4-Wire SPI Control of all functions On-Chip Programmable State Machines for fast multiplier/filter and transmitter switching and control On-chip temperature sensor, output power detectors, and ADC DC power: 450 mW (2.5 V supply) 6 mm 6 mm, 40-terminal LGA package

0.5 GHz to 19 GHz Broadband Bi-Directional Single Channel True Time Delay Unit Features:0.5 GHz to 19 GHz frequency rangeProgrammable Time Delay: 7-bit resolutionProgrammable Time Delay ModesTD_Mode0: 0 to 508ps range, 4ps Standard resolutionTD_Mode1: 0 to 254ps range, 2ps High resolutionProgrammable Attenuation: 6-bit resolution31.5 dB adjustment range0.5 dB step sizeFully programmable via a 3-wire or 4-wire SPI interfaceSPI Programmable and Daisy Chaining selectablePower Dissipation: 1 mW with 1.2V and 1.0V Dual Supplies14-pin 2x3mm LFCSP

SigmaDSP Digital Audio Processor Features: Qualified for automotive applications Fully programmable audio DSP for enhanced sound processing Features SigmaStudio, a proprietary graphical programming tool for the development of custom signal flows Clock oscillator for generating master clock from crystal Up to 294.912 MHz, 32-bit SigmaDSP core at 1.2 V Up to 6144 SIMD instructions per sample at 48 kHz Up to 40 kWords of parameter/data RAM Up to 800 ms digital audio delay pool at 48 kHz Audio input/output and routing 4 serial input ports, 4 serial output ports 48-channel, 32-bit digital input/output up to a sample rate of 192 kHz Flexible configuration for TDM, I2S, left and right justified formats, and PCM Up to 8 stereo ASRCs from 1:8 up to 7.75:1 ratio and 139 dB DNR Stereo S/PDIF input and output Four PDM microphone input channels Multichannel, byte addressable, TDM serial ports Integer PLL and flexible clock generators Integrated die temperature sensor

+2.5 V to 5.5 V, 400 A, Quad Rail-To-Rail Output 12-Bit DAC Features: Four 12-Bit DACS in 16-Lead TSSOP Low Power: 500 µA @ 5 V, 400 µA @ 3 V Power-Down to 300 nA @ 5 V, 90nA @ 3 V Guaranteed Monotonic by Design Power-On-Reset to Zero Volts Double-Buffered Input Logic Low Power, SPI™, QSPI™, MICROWIRE™ and DSP-Compatible 3-Wire Serial Interface Output Range: O-VREF or O-2VREF Simultaneous Update of DAC Outputs via LDAC pin (active low) Asynchronous Clear Facility via CLR pin (active low) SDO Daisy-Chaining Option Buffered/Unbuffered Reference Input Options for each DAC pair

8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: 3 power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification) Crosspoint multiplexed analog inputs 8 differential/15 pseudo differential inputs See data sheet for additional features

Low Power, 24-Bit, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers Features: Fast and flexible output rate: 1.25 SPS to 31.25 kSPS Channel scan data rate of 6.21 kSPS/channel (161 µs settling) Performance specifications 17.2 noise free bits at 31.25 kSPS 24 noise free bits at 5 SPS INL: ±2 ppm of FSR 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling User configurable input channels 2 fully differential channels or 4 single-ended channels Crosspoint multiplexer On-chip 2.5 V reference (±2 ppm/°C drift) True rail-to-rail analog and reference input buffers Internal or external clock See data sheet for additional features

4-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference Features: Three power modes RMS noise Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 μA typical) Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 μA typical) Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 μA typical) Up to 22 noise free bits in all power modes (gain = 1) Output data rate Full power: 9.38 SPS to 19,200 SPS Mid power: 2.34 SPS to 4800 SPS Low power: 1.17 SPS to 2400 SPS Rail-to-rail analog inputs for gains > 1 Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle settling) Diagnostic functions (which aid safe integrity level (SIL) certification Crosspoint multiplexed analog inputs 4 differential/7 pseudo differential inputs Programmable gain (1 to 128) Band gap reference with 10 ppm/°C drift maximum (70 μA) Matched programmable excitation currents Internal clock oscillator On-chip bias voltage generator Low-side power switch General-purpose outputs Multiple filter options Internal temperature sensor Self and system calibration Sensor burnout detection Automatic channel sequencer Per channel configuration Power supply: 2.7 V to 3.6 V and ±1.8 V Independent interface power supply Power-down current: 5 μA maximum Temperature range: −40°C to +125°C 32-lead LFCSP/24-lead TSSOP 3-wire or 4-wire serial interface SPI, QSPI, MICROWIRE, and DSP compatible Schmitt trigger on SCLK ESD: 4 kVAD7124-4-EP Supports defense and aerospace applications (AQEC standard) Download AD7124-4-EP Data Sheet (PDF) Full military temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request V62/19614

Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors Features:Pin-programmable output rateOutput data rate: 10 Hz, 50 Hz, 60 Hz, 120 HzPin-programmable PGAGain: 1, 8, 64, 128Pin-programmable power-down and resetRMS noise: 15 nV @ 10 Hz (gain = 128)Up to 21.5 noise free bits (gain = 1)Please see data sheet for additional features

14 Gbps, 2:1 Differential Selector with Programmable Output Voltage Features: Supports High Data Rates: up to 14 Gbps Differential or Single-Ended Operation Fast Rise and Fall Times: 19 / 20 ps Low Power Consumption: 221 mW typ Programmable Differential Output Voltage Swing: 500 - 1300 mVp-p Propagation Delay: 87 ps Single Supply: -3.3 V 24 Lead Ceramic 4x4 mm SMT Package: 16 mm2

CMOS 12-Bit Buffered Multiplying DAC With Onboard Data Latches Features: 12-Bit Resolution Low Gain TC: 2ppm/°C typ Fast TTL Compatible Data Latches Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount Packages Single +5 V to +15 V Supply Latch Free (Schottky Protection Diode not Required) Low Cost Ideal for Battery Operated Equipment