Silicon SPDT Switch, Reflective, 35 GHz to 44 GHz Features:Reflective design Low insertion loss: 1.8 dB at 44 GHz High isolation: 28 dB at 44 GHz High input linearity 0.1 dB power compression (P0.1dB): 37 dBm Third-order intercept (IP3): 52 dBm High RF power handling: 28 dBm average 36 dBm peak Single supply operation: 3.3V Internal negative voltage generator (NVG) RF settling time (0.1 dB final RF output): 45 ns 20-terminal, 3 mm × 3 mm, land grid array package Pin compatible with the ADRF5300: 24 GHz - 32 GHz

Dual-Channel, 3.7 GHz to 5.3 GHz, Receiver Front End Features: Integrated dual-channel RF front end 2-stage LNA and high power SPDT switch On-chip bias and matching Single supply operation Gain High gain mode: 33 dB typical at 4.6 GHz Low gain mode: 18 dB typical at 4.6 GHz Low noise figure High gain mode: 1.6 dB typical at 4.6 GHz Low gain mode: 1.6 dB typical at 4.6 GHz High channel to channel isolation  Between RxOUT-ChA and RxOUT-ChB: 45 dB typical Between TERM-ChA and TERM-ChB: 53 dB typical  Low insertion loss: 0.5 dB typical at 4.6 GHz High power handling at TCASE = 105°C Full lifetime LTE average power (9 dB PAR): 40 dBm Single event (<10 sec operation) LTE average power (9 dB PAR): 43 dBm High OIP3: 31 dBm typical Power-down mode and low gain mode for LNA Low supply current High gain mode: 86 mA typical at 5 V Low gain mode: 36 mA typical at 5 V Power-down mode: 12 mA typical at 5 V Positive logic control 40-lead, 6 mm × 6 mm LFCSP 

0.5 dB LSB, 6-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Features:Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 0.5 dB steps to 31.5 dB Low insertion loss with impedance match 2.1 dB up to 18 GHz 2.9 dB up to 26 GHz 4.8 dB up to 40 GHz Attenuation accuracy with impedance match ±(0.10 + 1.0% of attenuation state) up to 18 GHz ±(0.15 + 0.8% of attenuation state) up to 26 GHz ±(0.35 + 2.5% of attenuation state) up to 40 GHz Typical step error with impedance match ±0.18 dB up to 18 GHz ±0.23 dB up to 26 GHz ±0.51 dB up to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 27 dBm IP3: 50 dBm typical High RF input power handling: 27 dBm average, 30 dBm peak Tight distribution in relative phase No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF settling time (0.1 dB of final RF output): 250 ns 24-terminal, 4 mm × 4 mm LGA package Pin compatible with ADRF5720, low frequency cutoff version

2 dB LSB, 4-Bit, Silicon Digital Attenuator, 100 MHz to 40 GHz Features: Ultrawideband frequency range: 100 MHz to 40 GHz Attenuation range: 2 dB steps to 30 dB Low insertion loss 1.7 dB to 18 GHz 2.2 dB to 26 GHz 3.5 dB to 40 GHz Attenuation accuracy ±(0.1 + 2.0%) of attenuation state up to 18 GHz ±(0.2 + 2.5%) of attenuation state up to 26 GHz ±(0.5 + 10.0%) of attenuation state up to 40 GHz High RF input power handling: 26 dBm average, 30 dBm peak Tight distribution in relative phase Typical step error ±0.15 dB to 18 GHz ±0.20 dB to 26 GHz ±0.60 dB to 40 GHz High input linearity P0.1dB insertion loss state: 30 dBm P0.1dB other attenuation states: 26 dBm IP3: 50 dBm typical No low frequency spurious signals SPI and parallel mode control, CMOS/LVTTL compatible RF amplitude settling time (0.1 dB of final RF output): 230 ns 2.5 mm × 2.5 mm, 16-terminal LGA package Pin compatible with ADRF5721, low frequency cutoff version

15.1 GHz to 32 GHz, Tunable Band-Pass Filter Features:Amplitude settling time: 200 ns typicalWideband rejection: 30 dBSingle chip implementation40-lead, 6 mm 6 mm, RoHS compliant LFCSP

2 GHz to 18 GHz, Digitally Tunable, High-Pass and Low-Pass Filter Features: Digitally tunable, multioctave, high-pass and low-pass tuning Independent 3 dB frequency control for up to 4 GHz of bandwidth Optimal wideband rejection: 35 dB Single chip replacement for discrete filter banks Compact 9 mm × 9 mm, 56-terminal LGA packageENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard Military temperature range of −55°C to +105°C Controlled manufacturing baseline One assembly and test site One fabrication site Production change notification Qualification data available on request V62/21604

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp Features: Meets SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV Patented clock recovery architecture Loss-of-signal detect range: 3 mV to 15 mV Single-reference clock frequency for all rates, including15/14 (7%) wrapper rate Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK REFCLK inputs: LVPECL/LVDS/LVCMOS/LVTTL compatible (LVPECL/LVDS only at 155.52 MHz) Optional 19.44 MHz on-chip oscillator to be used with external crystal Loss-of-lock indicator Loopback mode for high speed test data Output squelch and bypass features Single-supply operation: 3.3 V Low power: 540 mW typical 7 mm × 7 mm, 48-lead LFCSP

5.7 kV RMS/1.5 kV RMS, Quad-Channel LVDS 2.5 Gigabit Isolator (0 Reverse Channels) Features: 5.7 kV rms and 1.5 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS signal levels Quad-channel configuration Any data rate up to 2.5 Gbps switching with low jitter 10 Gbps total bandwidth across four channels 2.15 ns typical propagation delay Typical jitter: 0.82 ps rms random, 40 ps total peak Lower power 1.8 V supplies ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: 100 kV/μs typical Safety and regulatory approvals (28-lead SOIC_W_FP package) UL (pending): 5700 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-11 (VDE V 0884-11):2017-01 VIORM = 849 VPEAK (working voltage) Enable or disable refresh (low speed output correctness check) Operating temperature range: −40°C to +125°C 28-lead, wide-body, finer pitch SOIC_W_FP package with 8.3 mm creepage and clearance or 6 mm × 6 mm LFCSP package with 1.27 mm creepage and clearance

5 kV RMS/3.75 kV RMS, Dual LVDS Gigabit Isolator (0 Reverse Channels) Features: 5 kV rms and 3.75 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS standard Multiple dual-channel configurations Any data rate up to 1.1 Gbps switching with low jitter 4 ns typical propagation delay 2.6 ps rms typical random jitter, rms 90 ps typical peak-to-peak total jitter at 1.1 Gbps 2.5 V or 3.3 V supplies −75 dBc power supply ripple rejection, phase spur level Glitch immunity ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: >25 kV/μs Passes EN 55022 Class B radiated emissions limits with 1.1 Gbps PRBS Safety and regulatory approvals (20-lead SOIC_W package) UL (pending): 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 VPEAK Fail-safe output high for open, short, and terminated input conditions (ADN4655/ADN4656) Operating temperature range: −40°C to +125°C 7.8 mm minimum creepage and clearance

5 kV RMS/3.75 kV RMS, Dual LVDS Gigabit Isolator (Second Channel Reversed) Features: 5 kV rms and 3.75 kV rms LVDS isolators Complies with TIA/EIA-644-A LVDS standard Multiple dual-channel configurations Any data rate up to 1.1 Gbps switching with low jitter 4 ns typical propagation delay 2.6 ps rms typical random jitter, rms 90 ps typical peak-to-peak total jitter at 1.1 Gbps 2.5 V or 3.3 V supplies −75 dBc power supply ripple rejection, phase spur level Glitch immunity ±8 kV IEC 61000-4-2 ESD protection across isolation barrier High common-mode transient immunity: >25 kV/μs Passes EN 55022 Class B radiated emissions limits with 1.1 Gbps PRBS Safety and regulatory approvals (20-lead SOIC_W package) UL (pending): 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice 5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 VPEAK Fail-safe output high for open, short, and terminated input conditions (ADN4655/ADN4656) Operating temperature range: −40°C to +125°C 7.8 mm minimum creepage and clearance