10-Bit, 4 Oversampling SDTV Video Decoder Features: Automotive versions qualified per AEC-Q100, Grade 1 Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit ADC, 4× oversampling for CVBS, 2× oversampling for Y/C mode, and 2× oversampling for YPrPb (per channel) 3 video input channels with on-chip antialiasing filter CVBS (composite), Y/C (S-video), and YPrPb (component) video input support 5-line adaptive comb filters and CTI/DNR video enhancement Adaptive Digital Line Length Tracking (ADLLT), signal processing, and enhanced FIFO management give mini-TBC functionality See data sheet for additional features

SMD Data Sheet

CMOS Low Voltage 2.5 Quad SPST Switch Features: 1.8 V to 5.5 V Single Supply 2.5 O (Typ) On Resistance Low On-Resistance Flatness -3 dB Bandwidth >200 MHz Rail-to-Rail Operation 16-Lead TSSOP/SOIC packages Fast Switching Times  tON 16 ns tOFF 10 ns Typical Power Consumption (<0.01 µW ) TTL/CMOS Compatible

6.2 GHz Fractional-N Frequency Synthesizer Features: RF bandwidth to 6.2 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with the ADF4110, ADF4111, ADF4112, ADF4113, ADF4106, ADF4153, and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADIsimPLL Cycle slip reduction for faster lock times

Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC Features: Complete quad, 16-bit digital-to-analog converters (DAC) Programmable output range: ±10 V, ±10.2564 V, or ±10.5263 V ±1 LSB max INL error, ±1 LSB maximum DNL error Low noise: 60 nV/√Hz Settling time: 10 µs maximum Integrated reference buffers Internal reference: 10 ppm/°C maximum On-chip die temperature sensor Output control during power-up/brownout Programmable short-circuit protection Simultaneous updating via LDAC Asynchronous CLR to zero code Digital offset and gain adjust See Data Sheet for Additional Information

2.7 V to 5.5 V, <100 A, 8-/10-/12-Bit nanoDACs with I2C-Compatible Interface in LFCSP and SC70

0.8% Accurate Quad UV/OV Positive/Negative Voltage Supervisor Features: Chinese data sheet availableQuad undervoltage/overvoltage (UV/OV) positive/negative supervisorSupervises up to two negative railsAdjustable UV and OV input thresholdsIndustry leading threshold accuracy over the extended temperature range: 0.8%1 V buffered reference outputOpen-drain UV and OV reset outputsAdjustable reset timeout with disable optionOutputs guaranteed down to VCC of 1 VPlease see data sheet for additional features

The ADIN1200 is a low power, single-port, 10 Mbps and 100 Mbps Ethernet transceiver with low latency specifications designedfor industrial Ethernet applications.This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated common analog circuitry, input and output clock buffering, management interface and subsystem registers, and media access control (MAC) interface and control logic to manage the reset, clock control and pin configuration.The ADIN1200 is available in a 5 mm ? 5 mm, 32-lead leadframe chip scale package (LFCSP) and can operate with a single3.3 V supply, assuming the use of a 3.3 V MAC interface supply.For maximum flexibility in system level design, a separate VDDIOsupply enables the management data input/output (MDIO) andMAC interface supply voltages to be configured independentlyof the other circuitry on the ADIN1200 allowing operation at1.8 V, 2.5 V, or 3.3 V. At power-up, the ADIN1200 is held inhardware reset until each of the supplies has crossed its minimumrising threshold value and the power is considered good. Brownoutprotection is provided by monitoring the supplies to detect ifone or more of them drops below a minimum falling thresholdand holding the device in hardware reset until the power suppliesreturn and satisfy the power-on-reset (POR) circuit.The MII management interface (also referred to as MDIOinterface) provides a 2-wire serial interface between a hostprocessor or MAC and the ADIN1200, allowing access tocontrol and status information in the PHY core managementregisters. The interface is compatible with both IEEE? 802.3?Standard Clause 22 and Clause 45 management framestructures.The ADIN1200 can support cable lengths up to 180 meters.Note that throughout this data sheet, multifunction pins, such as XTAL_I/CLK_IN/REF_CLK, are referred to either by the entire pin name or by a single function of the pin, for example, XTAL_I, when only that function is relevant.Applications Industrial automation Process control Factory automation Robotics and motion Control Building automation Test and Measurement Industrial internet of things (IoT)

ADI

ADI